IAETSD

1. POWER CAPTURE SAFE TEST PATTERN DETERMINATION
FOR AT-SPEED SCAN BASED TESTING
1
P.Praveen Kumar, 2
B.Naresh Babu, 3
N.Pushpalatha
M.Tech (DECS) Student, Assistant professor, Assistant professor
Department of ECE, AITS
Annamacharya Institute of Technology and Sciences, Tirupati, India-517520
1
pnani427@gmail.com
2
naresh.birudala@gamil.com
3
pushpalatha_nainaru@rediff.com
Abstract — Scan based test proves a better choice of
test methodology for testing digital circuits. During an
at-speed scan-based test, excessive capture power may
cause significant current demand, resulting in the IR-
drop problem and unnecessary yield loss. Many
methods address this problem by reducing the
switching activities of power-risky patterns. These
methods may not be efficient when the number of
power-risky patterns is large or when some of the
patterns require extremely high power. The proposed
method in this project discards all power-risky
patterns and starts with power-safe patterns only,
which includes two processes, namely, test pattern
refinement and low-power test pattern regeneration.
The test pattern refinement process is used to refine
the power-safe patterns to detect faults originally
detected only by power-risky patterns. If some faults
are still undetected after this process, the low power
test pattern regeneration process is applied to generate
new power-safe patterns to detect these faults. The
patterns obtained using the proposed procedure are
guaranteed to be power-safe for the given power
constraints. Among these, the first method refines only
the power-safe patterns to address the capture power
problem. The designs are verified using Verilog HDL
in Xilinx 10.1i Synthesizer for the Spartan 3E FPGA
Kit. The required test data volume can be reduced by
nearly 12.76% on average with little or no fault
coverage loss.
Index Terms—At-speed testing, low capture power
testing,
scan-based testing, transition fault.
I INTRODUCTION
SCAN-BASED testing is the most widely used
design for test (DFT) methodology due to its simple
structure, high fault coverage, and strong diagnostic
support. However, the test power of scan tests may
be significantly higher than normal functional
power because circuits may en ter non-functional
states during testing. The test power required to load
or unload test data with shift clock control is called
shift power, and the power required to capture test
responses with an at-speed clock rate is called
capture power. Excessive shift power can lead to
high temperatures that can damage the circuit under
test (CUT) and may reduce the circuit’s reliability.
Excessive capture power induced by test patterns
may lead to large current demand and induce a
supply voltage drop, known as the IR-drop problem.
This would cause a normal circuit to slow down and
eventually fail the test, thereby inducing
unnecessary yield loss.
To estimate shift power and capture power,
several metrics have been proposed.
1. The circuit level simulation metric
a. The most accurate one.
b. Time consuming and memory
intensive.
2. Most previous works use simpler metrics. The
toggle count metric considers the state changes
of nodes (FFs or gates) and the weighted
switching activity (WSA) metric considers both
node state changes and fanouts of nodes. Metrics
that consider paths are also proposed.
3. The critical capture transition (CCT) metric
assesses launch switching activities around
critical paths, and the critical area targeted
(CAT) metric estimates launch switching
activities caused by test patterns around the
longest sensitized path. In this paper, we will
employ the WSA metric as it is highly correlated
to the real capture power and has been used in
most related work to determine power-safe test
patterns.
4. The capture-power-safe patterns: To address the
capture-safe-power problem, numerous methods
have been proposed.
a) The hardware-based methods attempt to reduce
test power by modifying the circuit/clock in test
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2. structures or by adding some additional
hardware to the CUT.
I. In scan chain segmentation methods are
proposed to reduce both shift and capture
power.
II. In a partial launch on- capture (LOC) scheme
is proposed to reduce the capture power,
which allows only partial scan cells to be
activated during the capture cycle.
Advantages:
1. Some clock gating schemes have also been
proposed to limit the test power
consumption.
2. They effectively reduce test power.
Disadvantages:
1. They may increase circuit area
2. Degrade circuit performance
3. They may be incompatible with existing
design flows
b) software-based methods attempt to generate
power safe test patterns that will not consume
excess power during testing by modifying the
traditional automatic test pattern generation
(ATPG) procedure or by modifying
predetermined test sets. These methods are
generally based on the X-filling technique to
assign fixed logic values to don’t care bits (X-
bits) in test patterns to minimize test power
dissipation.
c) Instead of modifying the ATPG procedure, some
post-ATPG methods modify a given test set by
using X-filling to reduce as much test power as
possible [7], [10], [16] or to satisfy the power
constraints [6], [21], [26]. Butler et al. [16]
propose a method, named adjacency fill, which
assigns deterministic values to the X-bits in line
with the adjacent bit values to reduce shift
power.
d) Another method to reduce the capture power is
to use the circuit’s steady states to fill X-bits [7].
This method, called ACF in [7], first fills X-bit
randomly. Then, it applies a number of
functional clock cycles starting from the scan-in
state of a test.
e) Vector to obtain the final states and uses these
states to fill the X-bits to get more realistic
patterns. Although both the Preferred Fill and
the ACF methods can quickly assign the X-bits
in PPI, they cannot ensure capture power
safety because they do not consider the power
constraint of the circuit. Another problem with
the above two methods is that they try to
assign values to all X-bits in all test patterns to
reduce test power as much as possible.
However, not all of the test patterns are power-
risky [19].
I. Devanathan et al.and Wu et al. modified the
PODEM-based ATPG procedure by adding
some power constraints to the back trace and
dynamic compaction processes to directly
generate power-safe test sets.
II. In a low-capture power (LCP) X-filling method
is proposed and incorporated into the dynamic
compaction process of the test generation flow
to reduce the capture power.
III. Although these methods can achieve a large
reduction in capture power, they often increase
the test data volume in comparison with that
produced by conventional at-speed scan test
methods due to the fact that during the dynamic
compaction process, many X-bits that can be
assigned to detect more faults are reserved to
reduce capture power.
II METHODS TO REDUCE CAPTURE
POWER
1. Instead of modifying the ATPG procedure,
some post-ATPG methods modify a given
test set by using X-filling to reduce as
much test power as possible or to satisfy
the power constraints.
a) Adjacency fill assigns deterministic values
to the X-bits in line with the adjacent bit
values to reduce shift power.
eg,-given the test pattern (1, X, X, 1, 0), the
X-bits in this pattern are filled as (1, 1, 1,
1, 0).
b) The circuit’s steady states to fill X-bits
(ACF), this method first fills X-bit
randomly. Then, it applies a number of
functional clock cycles starting from the
scan-in state of a test vector to obtain the
final states and uses these states to fill the
X-bits to get more realistic patterns.
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3. Disadvantages:
1. Although both the Preferred Fill and the
ACF methods can quickly assign the X-bits
in PPI, they cannot ensure capture power
safety because they do not consider the
power constraint of the circuit.
2. They try to assign values to all X-bits in all test
patterns to reduce test power as much as
possible.
Fig.1: At-speed scan testing with LOC scheme.
III PROPOSED METHOD
This method modifies only power-safe
patterns to address the issue of the capture power.
The rationale behind this strategy is the patterns that
can detect more faults normally have larger
switching activity and lower X-bit ratios, and the
number of detected faults decreases drastically with
increasing X-bit ratio. Hence, filling X-bits in
power-risky patterns may not be efficient as they
tend to have lower X-bit ratios. In contrast, power-
safe patterns usually have higher X-bit ratios and
many unused X-bits. Therefore, using the X-bits in
power safe patterns to detect faults within the power
constraints may be more efficient than using those
in power-risky patterns.
Hence, this paper proposes a novel test pattern
determination procedure to determine a power safe
test set with the LOC clocking scheme.
The proposed procedure contains two processes
1. Test pattern refinement
2. Low-power test pattern regeneration
Given a pregenerated compacted partially-specified
test set without any power constraints, the power-
risky patterns are all dropped. This will make faults
that were detected only by the power risky patterns
become undetected. The test pattern refinement
process then tries to properly fill the X-bits in the
power safe patterns such that the power-risky faults
can be detected with the power constraint still being
satisfied. If some power risky faults remain
undetected after this process, the low-power test
pattern regeneration process is employed to generate
more power-safe test patterns for these faults.
CAPTURE-POWER-SAFE TEST PATTERN
DETERMINATION
This section first uses a simple example to illustrate
the main idea of the proposed procedure. Then, it
describes the overall flow and its details.
1) Main Idea
The main idea of this paper is to utilize the X-
bits in power-safe patterns to detect as many
faults that are previously detected only by
power-risky patterns as possible. If there are
still undetected faults, then a low-power pattern
generation process is used to generate patterns
to detect the remaining faults.
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4. 2) Overall Flow of Proposed Procedure
Based on the main idea, a technique is
proposed to determine a test set such that the
power constraint is satisfied and the test data
inflation is minimized
3) Algorithm for Test Pattern Refinement Process
1. The goal of the test pattern refinement
process is to utilize the X-bits in power-
safe patterns to to utilize the X-bits in
power-safe patterns to This process ends
when there are no remaining faults
In Fr or all the power-safe patterns in Ts have
been refined.
4) Algorithm for Low Power Test Generation
Process
The low-power test generation process
attempts to generate a new power-safe test
set to detect all the undetected faults and
minimize the test data inflation at the same
time. In order to achieve this goal, this
process uses a dynamic data compression
flow [20]
IV CONCLUSION AND FUTURE SCOPE
This paper proposed a novel capture-power-safe test
pattern determination procedure to address the
capture power problem. Unlike previous methods,
the test pattern refinement processing the proposed
procedure refines power-safe patterns to detect the
power-risky faults and discards the power-risky
patterns to ensure the capture power safety. The
capture power of newly generated patterns is also
guaranteed to be under the power constraints. The
experimental results show that more than 75% of
power-risky faults can be detected by refining the
power safe patterns, and that the required test data
volumes can be reduced by 12.76% on average
under the appropriate power constraints without
fault coverage loss.
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