1. Sequential Logic and
Flip-Flops

2. SEQUENTIAL CIRCUITS AND
FEEDBACK

3. SET- RESET (S-R) LATCHES :
Cross- NOR S-R latch ( active high )
 Cross- NAND S-R latch ( active low )


4. Cross-NOR S-R latch ( active high )

5. truth table of the NOR gate
A
B
(A + B)’
0
0
1
0
1
0
1
0
0
1
1
0
if any of the inputs of the
NOR gate is high (logic 1),
the output is low (logic 0)

6. No-Change condition in S-R
latch

7. Forbidden condition in S-R latch

8. function table of the NOR S-R
latch
R
S
Q
Q’
Comments
0
0
Q
Q’
0
1
1
0
No change ( hold )
condition
Set
1
0
0
1
Reset
1
1
0
0
Forbidden, Not used , race

9. the race situation



If we go from SR = 11 to SR = 00, then we may have two
cases.
Case 1: R changes first: SR = 10 then SR = 00
Case 2: S changes first: SR = 01 then SR = 00
1
1
0

10. Cross- NAND S-R latch
( active low ) – S’-R’

The truth table of NAND gate

12. Functions table of the NAND latch .

13. S – R Timing Analysis

14. EXAMPLE

If the S and R waveforms shown in Fig (11.a) are applied to
the inputs of the NOR latch, determine the waveform that will
be applied on the Q output. Assume that Q is initially low.

15. Switch Debouncing Circuits

Switch bounce occurs as a mechanical switch lever snaps to a
new position. After reaching the new contact point, the pole
bounces on a micrometer scale of millisecond duration (Fig
(12)). Bounce can cause problems in circuits that are expecting
an input to stabilize without oscillating, such as counters.

16. Debouncing using S’-R’ latch

When the switch is
neither connected
to the lower pin nor
to the upper pin,
both S’ and R’
equal + 5v ( Logic
1 ) and the latch is
in the no change
state .

17. Debouncing using S’-R’ latch
(cont.)

18. Clocked SR latches ( flip – flops )

19. clocked (gated) latch using cross –
NAND gates

20. Function table of gated S-R flip – flop

21. EXAMPLE

Determine the Q output waveform if the inputs
shown in Fig (17-a) are applied to a clocked
(gated) S-R latch that is initially RESET.

22. GATED D- latch

23. EXAMPLE

Sketch the output waveform at Q for the inputs
at D and G of the gated D latch in Fig (20).

24. EXAMPLE

Construct a D flip-flop using NOR and AND
gates.

25. J–K FLIP – FLOPS

26. J–K FLIP – FLOPS

28. T. (TOGGLE) FLIP–FLOP

29. Race problem in level-clocked J-K
flip-flop

30. Clock edge and level


edge – triggered FFs
Master – slave FFs .

31. MASTER – SLAVE FLIP-FLOPS

32. Timing diagram of a master-slave FF

33. EDGE – TRIGGERED J K FFS
+ve edge triggered
-ve edge triggered

34. EXAMPLE

Determine the Q
output waveform
if the inputs
shown in Fig
(32) are applied
to a clocked S-R
flip-flop that is
initially RESET.
The flip-flop is
triggered at the
positive edge.

35. MASTER-SLAVE FLIP-FLOP AND 1S
CATCHING

36. DIRECT ( ASYNCHRONOUS ) INPUTS

37. FLIP- FLOP OPERATING
CHARACTERISTICS

Propagation Delay times:


SET-UP TIME
HOLD TIME

38. Propagation Delay times:

39. Propagation Delay times:

40. SET-UP TIME

41. HOLD TIME