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VLSI
A 2.63 Mbit/S VLSI Implementation Of SISO Arithmetic Decoders For
High Performance Joint Source Channel Codes
3-D Mesh-Based Optical Network-On-Chip For Multiprocessor SystemOn-Chip
A Built-In Repair Analyzer With Optimal Repair Rate For WordOriented Memories
A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
A High-Speed Low-Complexity Modified FFT Processor For High Rate
WPAN Applications
A Low-Complexity Turbo Decoder Architecture For Energy-Efficient
Wireless Sensor Networks
A Meet-In-The-Middle Algorithm For Fast Synthesis Of Depth-Optimal
Quantum Circuits
AC-Plus Scan Methodology For Small Delay Testing And
Characterization
Addressing Transient And Permanent Faults In Noc With Efficient
Fault-Tolerant Deflection Router
All-Digital Fast-Locking Pulse Width-Control Circuit With
Programmable Duty Cycle
An Analytical Latency Model For Networks-On-Chip
An Energy-Efficient L2 Cache Architecture Using Way Tag
Information Under Write-Through Policy
An On-Chip Network Fabric Supporting Coarse-Grained Processor
Array
An Ultra Synchronization Checking Method With Trace-Driven
Simulation For Fast And Accurate MP Soc Virtual Platform Simulation
V15.Application Space Exploration Of A Heterogeneous Run-Time
Configurable Digital Signal Processor
Architecture For Real-Time Nonparametric Probability Density
Function Estimation
Built-In Generation Of Functional Broadside Tests Using A Fixed
Hardware Structure
A Built-In Self-Repair Scheme For 3-D Rams With Interdie
Redundancy
Check Pointing For Virtual Platforms And System C-TLM
Further more details visit: http://www.temasolution.com/
send your request to : info@temasolution.com
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2. 28,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43855940
Mobile : +91-8680802110 Web :
www.temasolution.com email :
temasolution@gmail.com
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Circuit-Level Timing Error Tolerance For Low-Power DSP Filters And
Transforms
Combined Architecture/Algorithm Approach To Fast FPGA Routing
CORDIC Designs For Fixed Angle Of Rotation
Design And Implementation Of An On-Chip Permutation Network For
Multiprocessor System-On-Chip
Design Of Digit-Serial FIR Filters: Algorithms, Architectures, And A
CAD Tool
Efficient Implementation Of Reconfigurable Warped Digital Filters
With Variable Low-Pass, High-Pass, Band Pass, And Band Stop
Responses
Error Detection In Majority Logic Decoding Of Euclidean Geometry
Low Density Parity Check (EG-LDPC) Codes
Exploration And Optimization Of 3-D Integrated DRAM Subsystems
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
Improved Trace Buffer Observation Via Selective Data Capture Using
2-D Compaction For Post-Silicon Debug
IsoNet: Hardware-Based Job Queue Management For Many-Core
Architectures
Joint Decoding Of LDPC Code And Phase Factors For OFDM Systems
With PTS PAPR Reduction
Low-Overhead Fault-Tolerance Technique for a Dynamically
Reconfigurable Softcore Processor
Latch-Based Performance Optimization For Field-Programmable Gate
Arrays
MDC FFT/IFFT Processor With Variable Length For MIMO-OFDM
Systems
Mining Hardware Assertions With Guidance From Static Analysis
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With
Bounded-Length Maze Routing
Novel MIMO Detection Algorithm For High-Order Constellations In
The Complex Domain
On The Fixed-Point Accuracy Analysis And Optimization Of
Polynomial Specifications
Pipelined Radix- Feed Forward FFT Architectures
Pragmatic Integration Of An SRAM Row Cache In Heterogeneous 3-D
Further more details visit: http://www.temasolution.com/
send your request to : info@temasolution.com
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3. 28,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43855940
Mobile : +91-8680802110 Web :
www.temasolution.com email :
temasolution@gmail.com
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DRAM Architecture Using TSV
Reconfigurable Adaptive Singular Value Decomposition Engine Design
For High-Throughput MIMO-OFDM Systems
Scalability Analysis Of Memory Consistency Models In Noc-Based
Distributed Shared Memory Socs
Scaling Energy Per Operation Via An Asynchronous Pipeline
Secure Dual-Core Crypto Processor For Pairings Over Barreto-Naehrig
Curves On FPGA Platform
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays
Self-Repairing Digital System With Unified Recovery Process Inspired
By Endocrine Cellular Communication
STBC-OFDM Downlink Baseband Receiver For Mobile WMAN
Techniques For Compensating Memory Errors In JPEG2000
Test Patterns Of Multiple SIC Vectors: Theory And Application In
BIST Schemes
The LUT-SR Family Of Uniform Random Number Generators For
FPGA Architectures
Theoretical Modeling Of Elliptic Curve Scalar Multiplier On LUTBased Fpgas For Area And Speed
A 2.63 Mbit/S VLSI Implementation Of SISO Arithmetic Decoders For
High Performance Joint Source Channel Codes
A Flexible And Customizable Architecture For The Relaxation Labeling
Algorithm
A Novel VLSI DHT Algorithm For A Highly Modular And Parallel
Architecture
An Adaptive Subsystem Based Algorithm For Channel Equalization In
A SIMO System
Binary Discrete Cosine And Hartley Transforms
Computing Two-Pattern Test Cubes For Transition Path Delay Faults
Design Of Hardware Function Evaluators Using Low-Overhead NonUniform Segmentation With Address Remapping
DS-CDMA Implementation With Iterative Multiple Access Interference
Cancellation
V60.FPGA-Based 40.9-Gbits/S Masked AES With Area Optimization
For Storage Area Network
Low-Resolution DAC-Driven Linearity Testing Of Higher Resolution
Further more details visit: http://www.temasolution.com/
send your request to : info@temasolution.com
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4. 28,South Usman Road,, TNagar,
Chennai-17. Ph : 044-43855940
Mobile : +91-8680802110 Web :
www.temasolution.com email :
temasolution@gmail.com
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Adcs Using Polynomial Fitting Measurements
Low-Cost FIR Filter Designs Based On Faithfully Rounded Truncated
Multiple Constant Multiplication/Accumulation
One Analog STBC-DCSK Transmission Scheme Not Requiring
Channel State Information
Reconfigurable Accelerator For The Word-Matching Stage Of
BLASTN
Reduced-Complexity LCC Reed–Solomon Decoder Based On Unified
Syndrome Computation
Scale-Free Hyperbolic CORDIC Processor And Its Application To
Waveform Generation
Scaling, Offset, And Balancing Techniques In FFT-Based BP Non
Binary LDPC Decoders
Two-Rate Based Low-Complexity Variable Fractional-Delay FIR Filter
Structures
VLSI Architectures For The 4-Tap And 6-Tap 2-D Daubechies Wavelet
Filters Using Algebraic Integers
VLSI Implementation Of A Low-Cost High-Quality Image Scaling
Processor
VLSI Implementation Of A Multi-Mode Turbo/LDPC Decoder
Architecture
An Efficient Interpolation-Based Chase BCH Decoder
Further more details visit: http://www.temasolution.com/
send your request to : info@temasolution.com
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