underground cable fault location using aruino,gsm&gps
Sushant
1. 1 Presented by :- SUSHANT MISHRA EC-2 Under the guidance of :- FinFETs: From Circuit to Architecture
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9. Logic Styles: NAND Gates SG-mode NAND IG-mode NAND LP-mode NAND IG/LP-mode NAND pull up bias voltage pull down bias voltage IG-mode pull up LP-mode pull down
10. Comparing Logic Styles † Average leakage current for two-input NAND gate (V dd = 1.0V) Design Mode Advantages Disadvantages SG Fastest under all load conditions High leakage † (1 μ A) LP Very low leakage (85nA), low switched capacitance Slowest, especially under load. Area overhead (routing) IG Low area and switched capacitance Unmatched pull-up and pull-down delays. High leakage (772nA) IG/LP Low leakage (337nA), area and switched capacitance Almost as slow as LP mode
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19. TCMS Extension Delay-minimized netlist Power : 283.6uW Area: 538 fins Power-optimized netlist Power : 149.9uW Area: 216 fins
21. Power-minimized vs Delay-minimized Netlists at 130% ATC TCMS TCMS (Single-Vth Dual-Vdd % reduction in dynamic power 53.3 49.8 51.4 % reduction in leakage power 95.8 95.7 95.8 % reduction in total power 67.6 65.3 66.3 % reduction in Fin-count 65.2 59.5 61.6