تصميم منطقي

1. Flip Flops
prepared by : Eng. Rania Elsadig
Sudan University of science and
Technology
College of Engineering
Biomedical Engineering Department
Digital Design II
Third year

2. Clock Signal
Sequential logic circuits have memory
Output is a function of input and present state
Sequential circuits are synchronized by a periodic “clock” signal

3. SR Flip Flop
SR (set-reset) flip-flop based on two nor gates

4. SR Flip Flop

5. Edge triggered flip-flop changes only
when the clock C changes
Edge Triggered Flip Flop

6. Exercise
For a given S and R inputs to SR flip-flop,
sketch the output signal Q
Q
t

7. Exercise

8. Positive Edge Triggered D Flip Flop
Positive-edge triggered flip-flop changes only
on the rising edge of the clock C

9. Positive Edge Triggered D Flip Flop Cont.

10. Exercise
The input D to a positive-edge triggered flip-flop is shown
Find the output signal Q
Q
t

11. Exercise

12. Positive Edge Triggered JK Flip Flop

13. Positive Edge Triggered JK Flip Flop Cont.

14. T ( Toggle) Flip Flop

15. +
T ( Toggle) Flip Flop Cont.

16. D flip-flop with asynchronous reset

17. 17
Master-slave D-type flip-flop
D Q
CLK
Input
Master D latch
D Q Output
Slave D latch
X
• How to make into negative edge-triggered D-
type flip-flop?

18. Analysis of Clocked Sequential Circuits
State diagrams:
• How do we characterize logic circuits?
– Combinational circuits: Truth tables
– Sequential circuits: State diagrams
• First draw the states
– States  Unique circuit configurations
• Second draw the transitions between states
– Transitions  Changes in state caused by inputs

19. Example1: A Sequential Circuit with D
Flip Flops

20. State Table for the Circuit (ex1)

21. State Diagram for the Circuit
(ex1)

22. Example2: A Sequential Circuit
with D Flip Flops

23. example3: A Sequential Circuit with JK
Flip Flops

24. State Table & Diagram for the
Circuit (ex3)

25. example4: A Sequential Circuit with T
Flip Flops

26. State Table for the Circuit (ex4)