SlideShare uma empresa Scribd logo
1 de 34
DESIGN AND
SIMULATION OF PLL &
DLL USING MATLAB
SIMULINK
MADE BY :- KARTIK PAL
(131029)
PHASE LOCKED LOOP (PLL)
INTRODUCTION
 What is a PLL?
 Block Diagram of PLL
 Parts of a PLL
 PLL Design in Simulink
• PLL Without divider design
• Waveform
• PLL With divider design
• Waveform
What is a PLL?
 A phase lock loop (PLL) is a control
system that generates an output signal
whose phase is related to the phase of an
input signal
Block Diagram
Parts of a PLL
 Phase Detector
 Filter
 Voltage Controlled Oscillator
 Programmable Counter/Divider
Parts of a PLL
 Phase Detector
 Acts as comparator
 Produces a voltage proportional to the phase difference
between input and output signal
 Voltage becomes a control signal
Parts of a PLL
 Filter
 Determines dynamic characteristics of PLL
 Specify Capture Range (bandwidth)
 Specify Tracking Range
 Receives signal from Phase Detector and filters accordingly
Parts of a PLL
 Voltage Controlled Oscillator
 Set tuning range
 Set noise margin
 Creates low noise clock oscillation
 Divider
 Divides the VCO output by the degree of the open loop gain
 Feedback loop allows phase comparison
Parts of a PLL
PLL Design in Simulink
PLL Without Divider design
Waveform
Input signal
Phase Detector
Control signal
Synthesized Signal
Spectrum Analyser
PLL With Divider Design
Waveform
Input signal
Phase Detector
Control signal
Synthesized Signal
Spectrum Analyser 1
DELAY LOCKED LOOP (DLL)
INTRODUCTION
 What is a DLL?
 Block Diagram of DLL
 Parts of a DLL
 DLL Design in Simulink
• DLL design
• Waveform
What is DLL?
A delay-locked loop (DLL) is a digital circuit similar to
a Phase-Locked Loop (PLL), with the main difference
being the absence of an internal voltage-controlled
oscillator(VCO), replaced by a voltage-controlled delay
line (VCDL).
Block Diagram
Parts of a PLL
 Phase Detector(PD)
 Charge pump(CP)
 Loop Filter(LF)
 Voltage Controlled Delay Line(VCDL)
Parts of a DLL
 Phase Detector(PD)
 Acts as comparator
 Produces a voltage proportional to the phase difference
between input and output signal
 Voltage becomes a control signal
Parts of a DLL
 Charge Pump(CP)
• The outputs of the PD are directly connected to the
inputs of CP, and CP prepares the input of LF which is
proportional to the width of the PD output signals
(inputs of CP).
• In Matlab Simulink, a simple adder can be used to
model CP
Parts of a DLL
 Loop Filter(LF)
• Loop filter is a simple integrator that performs integral
of the output signals from CP.
• In the other word the loop filter’s capacitor gets
charged or discharged if there is a time lead or time
lag between the reference signal and the output of the
delay line.
Parts of a DLL
Voltage Controlled Delay Line(VCDL)
• Voltage controlled delay line (VCDL) includes a chain of
delay cells.
• Usually all of the delay cells have the same structure.
• In locked condition, the output of the last delay stage is
exactly one cycle lagged from the reference clock (Vin).
DLL Design in Simulink
Waveform
Input signal & Output signal
PLL & DLL DESIGN IN SIMULINK MATLAB

Mais conteúdo relacionado

Mais procurados

Phase locked loop
Phase locked loop Phase locked loop
Phase locked loop
imengineer
 
Optimal reception-of-digital-signals
Optimal reception-of-digital-signalsOptimal reception-of-digital-signals
Optimal reception-of-digital-signals
xyxz
 
Metastability,MTBF,synchronizer & synchronizer failure
Metastability,MTBF,synchronizer & synchronizer failureMetastability,MTBF,synchronizer & synchronizer failure
Metastability,MTBF,synchronizer & synchronizer failure
prashant singh
 
Ofdm tutorial fuyun_ling_rev1
Ofdm tutorial fuyun_ling_rev1Ofdm tutorial fuyun_ling_rev1
Ofdm tutorial fuyun_ling_rev1
Fuyun Ling
 
Exp amplitude modulation (1)
Exp amplitude modulation (1)Exp amplitude modulation (1)
Exp amplitude modulation (1)
Sarah Krystelle
 

Mais procurados (20)

Frequency modulation
Frequency modulationFrequency modulation
Frequency modulation
 
Phase locked loop
Phase locked loopPhase locked loop
Phase locked loop
 
Digital modulation techniques
Digital modulation techniquesDigital modulation techniques
Digital modulation techniques
 
Phase locked loop
Phase locked loop Phase locked loop
Phase locked loop
 
Modulation Techniques for Mobile Radio
Modulation Techniques for Mobile RadioModulation Techniques for Mobile Radio
Modulation Techniques for Mobile Radio
 
Optimal reception-of-digital-signals
Optimal reception-of-digital-signalsOptimal reception-of-digital-signals
Optimal reception-of-digital-signals
 
Phase locked loop
Phase locked loopPhase locked loop
Phase locked loop
 
continuos phase frequency shift keying(cpfsk)
continuos phase frequency shift keying(cpfsk)continuos phase frequency shift keying(cpfsk)
continuos phase frequency shift keying(cpfsk)
 
Wmc diversity
Wmc diversityWmc diversity
Wmc diversity
 
Metastability,MTBF,synchronizer & synchronizer failure
Metastability,MTBF,synchronizer & synchronizer failureMetastability,MTBF,synchronizer & synchronizer failure
Metastability,MTBF,synchronizer & synchronizer failure
 
RF Module Design - [Chapter 4] Transceiver Architecture
RF Module Design - [Chapter 4] Transceiver ArchitectureRF Module Design - [Chapter 4] Transceiver Architecture
RF Module Design - [Chapter 4] Transceiver Architecture
 
Fm demodulation using zero crossing detector
Fm demodulation using zero crossing detectorFm demodulation using zero crossing detector
Fm demodulation using zero crossing detector
 
Cfo in ofdm
Cfo in ofdmCfo in ofdm
Cfo in ofdm
 
RF Transceivers
RF TransceiversRF Transceivers
RF Transceivers
 
Chapter1 slide
Chapter1 slideChapter1 slide
Chapter1 slide
 
Ofdm tutorial fuyun_ling_rev1
Ofdm tutorial fuyun_ling_rev1Ofdm tutorial fuyun_ling_rev1
Ofdm tutorial fuyun_ling_rev1
 
Exp amplitude modulation (1)
Exp amplitude modulation (1)Exp amplitude modulation (1)
Exp amplitude modulation (1)
 
Superhetrodyne receiver
Superhetrodyne receiverSuperhetrodyne receiver
Superhetrodyne receiver
 
OFDM Orthogonal Frequency Division Multiplexing
OFDM Orthogonal Frequency Division MultiplexingOFDM Orthogonal Frequency Division Multiplexing
OFDM Orthogonal Frequency Division Multiplexing
 
Adaptive equalization
Adaptive equalizationAdaptive equalization
Adaptive equalization
 

Destaque

Ee443 phase locked loop - presentation - schwappach and brandy
Ee443   phase locked loop - presentation - schwappach and brandyEe443   phase locked loop - presentation - schwappach and brandy
Ee443 phase locked loop - presentation - schwappach and brandy
Loren Schwappach
 
Ee443 phase locked loop - paper - schwappach and brandy
Ee443   phase locked loop - paper - schwappach and brandyEe443   phase locked loop - paper - schwappach and brandy
Ee443 phase locked loop - paper - schwappach and brandy
Loren Schwappach
 
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
Phase Locked Loop with Filter Banks for High Data Rate Satellite LinkPhase Locked Loop with Filter Banks for High Data Rate Satellite Link
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
chiragwarty
 
cv-sayed-electric engineer
cv-sayed-electric engineercv-sayed-electric engineer
cv-sayed-electric engineer
sayed rayan
 
Matlab HTI summer training course_Lecture2
Matlab HTI summer training course_Lecture2Matlab HTI summer training course_Lecture2
Matlab HTI summer training course_Lecture2
Mohamed Awni
 

Destaque (17)

Ee443 phase locked loop - presentation - schwappach and brandy
Ee443   phase locked loop - presentation - schwappach and brandyEe443   phase locked loop - presentation - schwappach and brandy
Ee443 phase locked loop - presentation - schwappach and brandy
 
Phase locked loop design
Phase locked loop designPhase locked loop design
Phase locked loop design
 
Ee443 phase locked loop - paper - schwappach and brandy
Ee443   phase locked loop - paper - schwappach and brandyEe443   phase locked loop - paper - schwappach and brandy
Ee443 phase locked loop - paper - schwappach and brandy
 
DPLL PRESENTATION
DPLL PRESENTATIONDPLL PRESENTATION
DPLL PRESENTATION
 
Gmid ruida
Gmid ruidaGmid ruida
Gmid ruida
 
Pg fabio louvatti
Pg   fabio louvattiPg   fabio louvatti
Pg fabio louvatti
 
Pll
PllPll
Pll
 
Controlador de ganho automático baseado numa plataforma FPGA
Controlador de ganho automático baseado numa plataforma FPGAControlador de ganho automático baseado numa plataforma FPGA
Controlador de ganho automático baseado numa plataforma FPGA
 
PHASE LOCKED LOOP FOR GSM 900
PHASE LOCKED LOOP FOR  GSM 900PHASE LOCKED LOOP FOR  GSM 900
PHASE LOCKED LOOP FOR GSM 900
 
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
Phase Locked Loop with Filter Banks for High Data Rate Satellite LinkPhase Locked Loop with Filter Banks for High Data Rate Satellite Link
Phase Locked Loop with Filter Banks for High Data Rate Satellite Link
 
Pll carrier synch f-ling_v1.2
Pll carrier synch f-ling_v1.2Pll carrier synch f-ling_v1.2
Pll carrier synch f-ling_v1.2
 
Phase lock loop (pll)
Phase lock loop (pll)Phase lock loop (pll)
Phase lock loop (pll)
 
IEEE REAL TIME MATLAP COMMUNICATION PROJECTS
IEEE REAL TIME MATLAP COMMUNICATION PROJECTSIEEE REAL TIME MATLAP COMMUNICATION PROJECTS
IEEE REAL TIME MATLAP COMMUNICATION PROJECTS
 
cv-sayed-electric engineer
cv-sayed-electric engineercv-sayed-electric engineer
cv-sayed-electric engineer
 
2
22
2
 
Matlab HTI summer training course_Lecture2
Matlab HTI summer training course_Lecture2Matlab HTI summer training course_Lecture2
Matlab HTI summer training course_Lecture2
 
Perez cante edgar fuzzy
Perez cante edgar   fuzzyPerez cante edgar   fuzzy
Perez cante edgar fuzzy
 

Semelhante a PLL & DLL DESIGN IN SIMULINK MATLAB

PLL.pptx In the synchronized or “locked”
PLL.pptx In the synchronized or “locked”PLL.pptx In the synchronized or “locked”
PLL.pptx In the synchronized or “locked”
VasuhiSamydurai1
 

Semelhante a PLL & DLL DESIGN IN SIMULINK MATLAB (20)

phase ppt.pptx
phase ppt.pptxphase ppt.pptx
phase ppt.pptx
 
Phase locked loop design
Phase locked loop designPhase locked loop design
Phase locked loop design
 
Presentation 3 PLL_Analog_digital.pptx
Presentation 3 PLL_Analog_digital.pptxPresentation 3 PLL_Analog_digital.pptx
Presentation 3 PLL_Analog_digital.pptx
 
Phase lockedLoop
Phase lockedLoopPhase lockedLoop
Phase lockedLoop
 
PLL
PLLPLL
PLL
 
PHASE LOCKED LOOP AND TIMER
PHASE LOCKED LOOP AND TIMERPHASE LOCKED LOOP AND TIMER
PHASE LOCKED LOOP AND TIMER
 
research_report (1)
research_report (1)research_report (1)
research_report (1)
 
LIC UNIT III.pptx
LIC UNIT III.pptxLIC UNIT III.pptx
LIC UNIT III.pptx
 
Chapter 10- Synchronisation.ppt
Chapter 10- Synchronisation.pptChapter 10- Synchronisation.ppt
Chapter 10- Synchronisation.ppt
 
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCODESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO
 
Sub157
Sub157Sub157
Sub157
 
Pll
PllPll
Pll
 
PLL.pptx In the synchronized or “locked”
PLL.pptx In the synchronized or “locked”PLL.pptx In the synchronized or “locked”
PLL.pptx In the synchronized or “locked”
 
wepik-phase-locked-loop-20230425014233.pdf
wepik-phase-locked-loop-20230425014233.pdfwepik-phase-locked-loop-20230425014233.pdf
wepik-phase-locked-loop-20230425014233.pdf
 
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency Synthesizer
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerSpur Reduction Of MB-OFDM UWB System using CMOS Frequency Synthesizer
Spur Reduction Of MB-OFDM UWB System using CMOS Frequency Synthesizer
 
IRJET- Design of Low Power PLL using Sleepy Inverter Five Stage Current Starv...
IRJET- Design of Low Power PLL using Sleepy Inverter Five Stage Current Starv...IRJET- Design of Low Power PLL using Sleepy Inverter Five Stage Current Starv...
IRJET- Design of Low Power PLL using Sleepy Inverter Five Stage Current Starv...
 
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
 
LIC-Unit-IV-PLL.pptx
LIC-Unit-IV-PLL.pptxLIC-Unit-IV-PLL.pptx
LIC-Unit-IV-PLL.pptx
 
Lf2418891896
Lf2418891896Lf2418891896
Lf2418891896
 
Synchronization
SynchronizationSynchronization
Synchronization
 

PLL & DLL DESIGN IN SIMULINK MATLAB

  • 1. DESIGN AND SIMULATION OF PLL & DLL USING MATLAB SIMULINK MADE BY :- KARTIK PAL (131029)
  • 3. INTRODUCTION  What is a PLL?  Block Diagram of PLL  Parts of a PLL  PLL Design in Simulink • PLL Without divider design • Waveform • PLL With divider design • Waveform
  • 4. What is a PLL?  A phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal
  • 6. Parts of a PLL  Phase Detector  Filter  Voltage Controlled Oscillator  Programmable Counter/Divider
  • 7. Parts of a PLL  Phase Detector  Acts as comparator  Produces a voltage proportional to the phase difference between input and output signal  Voltage becomes a control signal
  • 8. Parts of a PLL  Filter  Determines dynamic characteristics of PLL  Specify Capture Range (bandwidth)  Specify Tracking Range  Receives signal from Phase Detector and filters accordingly
  • 9. Parts of a PLL  Voltage Controlled Oscillator  Set tuning range  Set noise margin  Creates low noise clock oscillation
  • 10.  Divider  Divides the VCO output by the degree of the open loop gain  Feedback loop allows phase comparison Parts of a PLL
  • 11. PLL Design in Simulink PLL Without Divider design
  • 24. INTRODUCTION  What is a DLL?  Block Diagram of DLL  Parts of a DLL  DLL Design in Simulink • DLL design • Waveform
  • 25. What is DLL? A delay-locked loop (DLL) is a digital circuit similar to a Phase-Locked Loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator(VCO), replaced by a voltage-controlled delay line (VCDL).
  • 27. Parts of a PLL  Phase Detector(PD)  Charge pump(CP)  Loop Filter(LF)  Voltage Controlled Delay Line(VCDL)
  • 28. Parts of a DLL  Phase Detector(PD)  Acts as comparator  Produces a voltage proportional to the phase difference between input and output signal  Voltage becomes a control signal
  • 29. Parts of a DLL  Charge Pump(CP) • The outputs of the PD are directly connected to the inputs of CP, and CP prepares the input of LF which is proportional to the width of the PD output signals (inputs of CP). • In Matlab Simulink, a simple adder can be used to model CP
  • 30. Parts of a DLL  Loop Filter(LF) • Loop filter is a simple integrator that performs integral of the output signals from CP. • In the other word the loop filter’s capacitor gets charged or discharged if there is a time lead or time lag between the reference signal and the output of the delay line.
  • 31. Parts of a DLL Voltage Controlled Delay Line(VCDL) • Voltage controlled delay line (VCDL) includes a chain of delay cells. • Usually all of the delay cells have the same structure. • In locked condition, the output of the last delay stage is exactly one cycle lagged from the reference clock (Vin).
  • 32. DLL Design in Simulink
  • 33. Waveform Input signal & Output signal