In designing a system, we can replace cell components by appropriate technique based cell so that the noise margin of overall circuit is improved. In future we can also implement some techniques for sequential circuits.

1. Achintya Priydarshi & Manju K. Chattopaadhyay
School of Electronics
Devi Ahilya University , Indore
M.P. India
Performance Analysis of Encoder in Different
Logic Techniques for High-Speed & Low-Power
Application

2. CONTENTS
INTRODUCTION
LITERATURE REVIEW
EVOLUTION OF TECHNIQUE
COMPARISON OF RESULTS
CONCLUSION
FUTURE ENHANCEMENT
REFERENCES

3. INTRODUCTION
 Standard CMOS logic is slower and takes larger area.
Domino logic circuits are extensively used in high performance
digital implementation.
Due to their superior speed characteristics.
Domino logic circuits are extremely susceptible to noise and are
highly leaky.
 AVL (Adaptive Voltage Level) circuit technique and body bias
technique which will reduce leakage power as well as improve
the noise immunity.

4. LITERATURE REVI
Domino Logic
AVL circuit technique
Body bias technique

5. PRE-CHARGE EVALUATION LOGIC
In dynamic CMOS logic a single clock φ can
be used to accomplish both the pre-charge
and evaluation operations.
When clock is low, PMOS pre-charge
transistor is turn on, output becomes high.
When clock goes high, PMOS is turned off
and the NMOS transistor is turned on, allow
the output to be selectively discharged to
GND depending on the logic inputs.

6. STATIC CMOS LOGIC
Low power
Only leakage when not switching
High Noise Tolerance
No clock needed
High fan-out load (lower speed)
 pFET and nFET loads
High noise generation

7. DOMINO LOGIC
The problem with faulty discharge of pre-charged nodes in CMOS
dynamic logic circuits can be solved by placing an inverter in series
with the output of each gate.

8. 
An elegant solution to the dynamic CMOS logic erroneous evaluation
problem is to use NP Domino Logic as shown below.

9. ADAPTIVE VOLTAGE LEVEL CIRCUIT
TECHNIQUE
Consists of a single p-MOS switch and m number of series
connected n-MOS switches.
Reduces the drain-source voltage appearing across the load
circuit.

10. BODY BIASING TECHNIQUE
 The voltage applied to the substrate affects the threshold voltage of a
MOSFET.
The voltage difference between the source and the subs-trate, VBS
changes the threshold voltage.

11. DOMINO INVERTER STATIC INVERTER

12. BODY BIAS INVERTER AVL INVERTER

13. IMPLEMENTATION OF 4-INPUT
NOR GATE

14. Static NOR
D

15. Domino NOR
a

16. AVL NOR

17. Body Bias NOR

18. IMPLEMENTATION OF 8×3
ENCODER

19. STATIC ENCODER
DOMINO DECODER

20. BODY BIAS ENCODER AVL ENCODER

21. COMPARISION OF POWER CONSUMPTION

22. COMPARISION OF NMH & NML

23. CONCLUSION
 AVL circuit technique consume less dynamic power than
the others.
 AVL technique requires large number of transistors to
implement the encoder which increases the complexity of
the circuit.
Body biasing increases the threshold voltage of the circuit
both of these techniques help to improve the noise margin
of the circuit. But it has highest dynamic and static power
consumption.
In this paper, we observed that encoder based on AVL
technique is better as compare to other because there is
comparatively less power consumption and it has high
noise margin.

24. FUTURE ENHANCEMENT
We have designed a cell library for combinational circuits,
like Inverter, NOR gate and 8×3 Encoder.
In designing a system, we can replace cell components by
appropriate technique based cell so that the noise margin
of overall circuit is improved.
In future we can also implement some techniques for
sequential circuits.

25. REFERENCES
[1] R. H. Krambeck, C. M. Lee, H. S. Law, High-Speed Compact Circuits with CMOS, IEEE
Journal of Solid State Circuits, pp.614-619, Vol. SC-17, No.3, June 1982.
[2] N. F. Goncalves, H. J. Deman, NORA: A Race Free Dynamic CMOS Technique for
Pipelined Logic Structures , IEEE Journal of Solid State‖
Circuits, pp.261-266, Vol.18, No.3, June 1983.
[3] Park, J. C., Mooney, Sleepy Stack Leakage Reduction Very Large Scale Integration (VLSI)
Systems, IEEE Transactions, pp.1250-1263, vol.14, No.1, November 2006.
[4] S. Kang, Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 3rd
ed, The
McGraw-Hill Companies, New Delhi, 2005.

26. [5] Dhananjay, E. Upasani, Sandip, B. Shrote, Pallavi, S. Deshpande, Standby Leakage Reduction in
Nanoscale CMOS VLSI Circuits, International journal of computer application, pp.1-4, Vol.7, No.5,
September 2010.
[6] R. K. Brayton, R. L. Rudell, A. L. Sangiovanni-Vincentelli, A Multiple-Level Logic Optimization
System , IEEE Trans. on Computer Aided Design, pp. 1062-1081, Vol.6, No.6, June 1987.‖
[7] P. Raikwal, M.Tech Thesis, School of Electronics, Devi Ahilya University, 2012.