The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes.
The objectives of this module are to demonstrate, within an embedded development environment:
• Processor – to – processor communication
• Multiple processors to perform one computation task using parallel processing
This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.
In other words, sequential logic has storage ( memory )
Std_logic_vector an unconstrained array
Std_logic_vector an unconstrained array
Use Ieee.numeric_std.all
C <= std_logic_vector (B)
Integer -2**31 to +2**31 - 1
Integer -2**31 to +2**31 - 1
Integer -2**31 to +2**31 - 1
suspends process/subprogram execution until a signal changes, a condition becomes true, or a defined time period has elapsed. Combinations of these can also be used.
See page 77 book
See page 77 book
All the SAS that we have seen so far, we have always assigned a single value to a signal Any arbitrary waveform can be easily created using a SAS The delay must appear in increasing order
When an assertion violation occurs, the report is issued and displayed on the screen. The severity level defines the degree to which the violation of the assertion affects operation of the process Note: provides information about the progress of the simulation
The message is displayed when the condition is NOT met
A test bench is a specification in VHDL that plays the role of a complete simulation environment for the analysed system (Unit Under Test, UUT). The test bench contains both the UUT as well as stimuli for the simulation. The UUT is instantiated as a component of the test bench and the architecture of the test bench specifies stimuli for the UUT’s ports.
Most simulators provide commands to apply stimulus to the input ports of a design entity. By tracing and viewing the resulting values of the signals on the output ports, we can determine whether the model is operating correctly. In VHDL, the model (test bench) generates sequences of inputs and reads the outputs of the module being tested.
-- Declare any libraries that will be needed -- Declare the packages that will be use in these libraries