4. DATA PATH
• Capable of performing certain operation on data
• Athematic Logic Unit
• External Busses & Internal Busses
• Both can have different design
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7. THREE-BUS ORGANIZATION
• Three Bus
• Two In-bus & one Out-bus design
• More busses will have data transfer faster
• More complex hardware design
• Expensive
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10. INTERRUPTS
• Mechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processing
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller
• Hardware failure
• e.g. memory parity error
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11. IF INTERRUPTS
•Suspend execution of current program
•Save context
•Set PC to start address of interrupt
handler routine
•Process interrupt
•Restore context and continue interrupted
program
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13. IF INTERRUPTS
•Suspend execution of current program
•Save context
•Set PC to start address of interrupt
handler routine
•Process interrupt
•Restore context and continue interrupted
program
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16. CONTROL UNIT
• Part of CPU
• Management of Computer Resources
• Control and Timing Signals
• Directs Flow of Data
• CU Types
• Mircoprogrammed
• Hardwire
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17. MICROPROGRAMMED
• Memory Units storing Control Signals
• Inaccessible Memory Units in RAM or ROM
• Control Word is microinstruction
• Microinstruction = 1/More Microoperations
• Sequence of microinstructions are microprograms
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19. CHAPTER REVIEW
• Fundamentals of Computer Organization and
Architecture by Mostafa Abd-Al-Barr & Hesham
AlRewini
• Chapter # 5
• CPU Basics
• Register Set
• Datapath
• CPU Instruction Cycle
• Control Unit
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