![Effect of the vias geometry on the Q factor of integrated
shunted inductors
J. Aguilera, F. Rodríguez, J. de No, J. Meléndez, R. Berenguer, J.R. Sendra, J. del Pino and A.
Hernández,
Dep. Ingeniería Electrónica y Automática / Instituto Universitario de Microelectrónica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria, Spain.
Publicated in Microwave Engineering,
vol. - pp. 35-37,
2002.
Abstract
For introducing SiGe standard processes in radio frequency applications, the performance of high quality
integrated inductors is an important task that should be solved. As it has been proofed in the bibliography [1]-[6],
the use of two or more metal layers connected in parallel improves the quality factor of the inductor. These layers
are shunted using vias that can adopt different geometries along the metal strip. This paper deals with the question
of how should these vias be laid out in a two metal SiGe 0.8 µm technology.
Via Model
Measurements & Simulations
Figure 3. Equivalent circuit of two metals connected by via
Figure 2. Simulated inductance vs frequency for four different via geometries and
Simulated resistance vs frequency for four different via geometries.
0
Figure 9. Inductance vs frequency measurements for five different via geometries
and Figure 10. Quality vs frequency measurements for five different via geometries.
Figure 7. Microphotograph of the five fabricated inductors.
Conclusions
From the simulation results, it may be concluded that the
resistance of the whole device decreases appreciably as
the size of the via is increased. The inductance also
decrease very slightly. So, the quality of the inductors
increase with the via area, as it was expected.
In order to verify the conclusions of the simulations, five
inductors were fabricated in a standard two metal SiGe
process 0.8 µm with different vias configuration. The
measurements confirm the simulations: the bigger the
Figure 4. Five different vias configuration
are of the via, the higher is the quality factor.
INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA)
UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)](https://image.slidesharecdn.com/effectoftheviasgeometryontheqfactorofintegratedshuntedinductors-121030054915-phpapp02/85/Effect-of-the-Vias-Geometry-on-the-Q-factor-of-Integrated-Shunted-Inductors-1-320.jpg?cb=1352363346)
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Effect of the Vias Geometry on the Q factor of Integrated Shunted Inductors
- 1. Effect of the vias geometry on the Q factor of integrated shunted inductors J. Aguilera, F. Rodríguez, J. de No, J. Meléndez, R. Berenguer, J.R. Sendra, J. del Pino and A. Hernández, Dep. Ingeniería Electrónica y Automática / Instituto Universitario de Microelectrónica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria, Spain. Publicated in Microwave Engineering, vol. - pp. 35-37, 2002. Abstract For introducing SiGe standard processes in radio frequency applications, the performance of high quality integrated inductors is an important task that should be solved. As it has been proofed in the bibliography [1]-[6], the use of two or more metal layers connected in parallel improves the quality factor of the inductor. These layers are shunted using vias that can adopt different geometries along the metal strip. This paper deals with the question of how should these vias be laid out in a two metal SiGe 0.8 µm technology. Via Model Measurements & Simulations Figure 3. Equivalent circuit of two metals connected by via Figure 2. Simulated inductance vs frequency for four different via geometries and Simulated resistance vs frequency for four different via geometries. 0 Figure 9. Inductance vs frequency measurements for five different via geometries and Figure 10. Quality vs frequency measurements for five different via geometries. Figure 7. Microphotograph of the five fabricated inductors. Conclusions From the simulation results, it may be concluded that the resistance of the whole device decreases appreciably as the size of the via is increased. The inductance also decrease very slightly. So, the quality of the inductors increase with the via area, as it was expected. In order to verify the conclusions of the simulations, five inductors were fabricated in a standard two metal SiGe process 0.8 µm with different vias configuration. The measurements confirm the simulations: the bigger the Figure 4. Five different vias configuration are of the via, the higher is the quality factor. INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA) UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)