This document discusses biasing circuits for BJTs. It begins by explaining that biasing circuits apply DC voltages to establish fixed operating points for transistors. This allows them to operate in the linear region. It then discusses several common biasing circuits: fixed bias, emitter-stabilized bias, and voltage divider bias. The fixed bias circuit uses two resistors and provides DC paths. The emitter-stabilized bias adds a resistor at the emitter for improved stability. The voltage divider bias uses a voltage divider network to provide DC voltages, making the operating point largely independent of transistor beta. It analyzes examples of each circuit type and discusses how to determine key voltages and currents like the Q-point, VCE, and

1. Chapter 2
BJT BIASING CIRCUIT

2. Introduction – Biasing
The analysis or design of a transistor amplifier requires knowledge of both the
dc and ac response of the system. In fact, the amplifier increases the strength
of a weak signal by transferring the energy from the applied DC source to the
weak input ac signal The analysis or design of any electronic amplifier therefore
has two components:
•The dc portion and
•The ac portion
During the design stage, the choice of parameters for the required dc levels
will affect the ac response.
Whatis biasing circuit?
Biasing:Application of dc voltages to establish a fixed level of current and
voltage.

3. Purpose of the DC biasing circuit
• To turn the device “ON”
• To place it in operation in the region of its characteristic where the device
operates most linearly .
•Proper biasing circuit which it operate in linear region and circuit
have centered Q-point or midpoint biased
•Improper biasing cause Improper biasing cause
•„
Distortionin the output signal
•„
Produce limited or clipped at output signal
Important basic relationship
E C B
I I I
= +
C
B
I
I
β =
( 1)
E B C
I I I
β
= + ≅
CB CE BE
V V V
= −

4. Operating Point
•Active or Linear Region Operation
Base – Emitter junction is forward biased
Base – Collector junction is reverse biased
Goodoperatingpoint
•Saturation Region Operation
Base – Emitter junction is forward biased
Base – Collector junction is forward
biased
•Cutoff Region Operation
Base – Emitter junction is reverse biased

5. BJT
Analysis
DC
analysis
Calculate the DC Q-point
solving input and
output loops
Graphical
Method
AC
analysis
Calculate gains of the
amplifier
DC Biasing Circuits
•Fixed-bias circuit
•Emitter-stabilized bias circuit
•Collector-emitter loop
•Voltage divider bias circuit
•DC bias with voltage feedback

6. FIXED BIAS CIRCUIT
 This is common emitter (CE)
configuration
 1st step: Locate capacitors and
replace them with an open
circuit
 2nd step: Locate 2 main loops
which;
BE loop (input loop)
CE loop(output loop)

7. FIXED BIAS CIRCUIT
 1st step: Locatecapacitors and replace them with an open
circuit

8. FIXED BIAS CIRCUIT
 2nd step: Locate 2 main loops.
1
2
1
2
BE Loop CE Loop

9. FIXED BIAS CIRCUIT
 BE Loop Analysis
1
■ From KVL;
IB
0
CC B B B
CC BE
B
B
E
V V
I
V
R
V I R
−
−
∴ =
+ + =
A

10. FIXED BIAS CIRCUIT
 CE Loop Analysis
■ From KVL;
■ As we known;
■ Substituting with
B
C I
I β
=
2
IC
0
CC C C CE
CE CC C C
V I R V
V V I R
− + + =
∴ = −
B
A B







 −
=
B
BE
CC
DC
C
R
V
V
I β
Note that does not affect the value of Ic
C
R

11. FIXED BIAS CIRCUIT
 DISADVANTAGE
Unstable– because it is too dependent on β and produce
width change of Q-point
For improved bias stability , add emitter resistor to dc bias.

12. Collector–Emitter Loop
The collector–emitter section of the network appears in Fig. 4.5 with the indicated
direction of current IC and the resulting polarity across RC. The magnitude of the col-
lector current is related directly to IB through
IC ⫽ ␤IB (4.5)
It is interesting to note that since the base current is controlled by the level of RB
and IC is related to IB by a constant ␤, the magnitude of IC is not a function of the
resistance RC. Change RC to any level and it will not affect the level of IB or IC as
long as we remain in the active region of the device. However, as we shall see, the
level of RC will determine the magnitude of VCE, which is an important parameter.
Applying Kirchhoff’s voltage law in the clockwise direction around the indicated
closed loop of Fig. 4.5 will result in the following:
VCE ⫹ ICRC ⫺ VCC ⫽ 0
and VCE ⫽ VCC ⫺ ICRC (4.6)
which states in words that the voltage across the collector–emitter region of a tran-
sistor in the fixed-bias configuration is the supply voltage less the drop across RC.
As a brief review of single- and double-subscript notation recall that
VCE ⫽ VC ⫺ VE (4.7)
where VCE is the voltage from collector to emitter and VC and VE are the voltages
from collector and emitter to ground respectively. But in this case, since VE ⫽ 0 V,
we have
VCE ⫽ VC (4.8)
In addition, since
VBE ⫽ VB ⫺ VE (4.9)
and VE ⫽ 0 V, then
VBE ⫽ VB (4.10)
Keep in mind that voltage levels such as VCE are determined by placing the red
(positive) lead of the voltmeter at the collector terminal with the black (negative) lead
at the emitter terminal as shown in Fig. 4.6. VC is the voltage from collector to ground
and is measured as shown in the same figure. In this case the two readings are iden-
tical, but in the networks to follow the two can be quite different. Clearly under-
standing the difference between the two measurements can prove to be quite impor-
tant in the troubleshooting of transistor networks.
Determine the following for the fixed-bias configuration of Fig. 4.7.
(a) IBQ
and ICQ
.
(b) VCEQ
.
(c) VB and VC.
(d) VBC.
147
4.3 Fixed-Bias Circuit
EXAMPLE 4.1
Figure 4.5 Collector–emitter
loop.
Figure 4.6 Measuring VCE and
VC.

13. Solution
(a) Eq. (4.4): IBQ
⫽ ᎏ
VCC
R
⫺
B
VBE
ᎏ ⫽ ᎏ
12
2
V
40
⫺
k
0
⍀
.7 V
ᎏ ⫽ 47.08 ␮A
Eq. (4.5): ICQ
⫽ ␤IBQ
⫽ (50)(47.08 ␮A) ⫽ 2.35 mA
(b) Eq. (4.6): VCEQ
⫽ VCC ⫺ ICRC
⫽ 12 V ⫺ (2.35 mA)(2.2 k⍀)
⫽ 6.83 V
(c) VB ⫽ VBE ⫽ 0.7 V
VC ⫽ VCE ⫽ 6.83 V
(d) Using double-subscript notation yields
VBC ⫽ VB ⫺ VC ⫽ 0.7 V ⫺ 6.83 V
⫽ ⴚ6.13 V
with the negative sign revealing that the junction is reversed-biased, as it should be
for linear amplification.
Transistor Saturation
The term saturation is applied to any system where levels have reached their maxi-
mum values. A saturated sponge is one that cannot hold another drop of liquid. For
a transistor operating in the saturation region, the current is a maximum value for the
particular design. Change the design and the corresponding saturation level may rise
or drop. Of course, the highest saturation level is defined by the maximum collector
current as provided by the specification sheet.
Saturation conditions are normally avoided because the base–collector junction is
no longer reverse-biased and the output amplified signal will be distorted. An oper-
ating point in the saturation region is depicted in Fig. 4.8a. Note that it is in a region
where the characteristic curves join and the collector-to-emitter voltage is at or be-
low VCEsat
. In addition, the collector current is relatively high on the characteristics.
If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick,
direct method for determining the saturation level becomes apparent. In Fig. 4.8b, the
current is relatively high and the voltage VCE is assumed to be zero volts. Applying
Ohm’s law the resistance between collector and emitter terminals can be determined
as follows:
RCE ⫽ ᎏ
V
I
C
C
E
ᎏ ⫽ ᎏ
0
IC
V
sat
ᎏ ⫽ 0 ⍀
148 Chapter 4 DC Biasing—BJTs
Figure 4.7 dc fixed-bias cir-
cuit for Example 4.1.

14. EMITTER-STABILIZED BIAS CIRCUIT
 An emitter resistor, RE is
added to improve stability
 1st step: Locatecapacitors and
replace them with an open
circuit
 2nd step: Locate 2 main loops
which;
BE loop
CE loop
Resistor,RE added

15. EMITTER-STABILIZED BIAS CIRCUIT
 1st step: Locatecapacitors and replace them with an open
circuit

16. EMITTER-STABILIZED BIAS CIRCUIT
 2nd step: Locate 2 main loops.
1
2
2
BE Loop CE Loop
1

17. EMITTER-STABILIZED BIAS CIRCUIT
 BE Loop Analysis
■ From kvl;
Recall;
Substitutefor IE
0
CC B B BE E E
V I R V I R
− + + + =
( 1) 0
( 1)
CC B B BE B E
CC BE
B
B E
V I R V I R
V V
I
R R
β
β
− + + + + =
−
∴ =
+ +
B
E I
I )
1
( +
= β
1

18. EMITTER-STABILIZED BIAS CIRCUIT
 CE Loop Analysis
■ From KVL;
■ Assume;
■ Therefore;
C
E I
I ≈
0
CC C C CE E E
V I R V I R
− + + + =
2
)
( E
C
C
CC
CE R
R
I
V
V +
−
=
∴

19. Improved Bias Stability
The addition of the emitter resistor to the dc bias of the BJT provides improved
stability, that is, the dc bias currents and voltages remain closer to where they
were set by the circuit when outside conditions, such as temperature, and
transistor beta, change.
( 1)
CC BE
c
B E
V V
I
R R
β
β
 
−
=  
+ +
 
Without Re With Re
CC BE
c
B
V V
I
R
β
 
−
=  
 
Note :it seems that beta in numerator canceled with beta in
denominator

20. For the emitter bias network of Fig. 4.22, determine:
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.
155
4.4 Emitter-Stabilized Bias Circuit
Solution
(a) Eq. (4.17): IB ⫽ ᎏ
RB
V
⫹
CC
(␤
⫺
⫹
VB
1
E
)RE
ᎏ ⫽
⫽ ᎏ
4
1
8
9
1
.3
k
V
⍀
ᎏ ⫽ 40.1 ␮A
(b) IC ⫽ ␤IB
⫽ (50)(40.1 ␮A)
⬵ 2.01 mA
(c) Eq. (4.19): VCE ⫽ VCC ⫺ IC (RC ⫹ RE)
⫽ 20 V ⫺ (2.01 mA)(2 k⍀ ⫹ 1 k⍀) ⫽ 20 V ⫺ 6.03 V
⫽ 13.97 V
(d) VC ⫽ VCC ⫺ ICRC
⫽ 20 V ⫺ (2.01 mA)(2 k⍀) ⫽ 20 V ⫺ 4.02 V
⫽ 15.98 V
(e) VE ⫽ VC ⫺ VCE
⫽ 15.98 V ⫺ 13.97 V
⫽ 2.01 V
or VE ⫽ IERE ⬵ ICRE
⫽ (2.01 mA)(1 k⍀)
⫽ 2.01 V
(f) VB ⫽ VBE ⫹ VE
⫽ 0.7 V ⫹ 2.01 V
⫽ 2.71 V
(g) VBC ⫽ VB ⫺ VC
⫽ 2.71 V ⫺ 15.98 V
⫽ ⴚ13.27 V (reverse-biased as required)
20 V ⫺ 0.7 V
ᎏᎏᎏ
430 k⍀ ⫹ (51)(1 k⍀)
EXAMPLE 4.4
Figure 4.22 Emitter-stabilized
bias circuit for Example 4.4.

21. VOLTAGE DIVIDER BIAS CIRCUIT
 Provides good Q-point stability with a single polarity supply voltage
 This is the biasing circuit wherein, ICQ and VCEQ are almostindependent of
beta.
 The level of IBQ will change with beta so as to maintain the values of ICQ and
VCEQ almostsame, thus maintaining the stability of Q point.
 Two methods of analyzing a voltage divider bias circuit are:
 Exact method : can be applied to any voltage divider circuit
 Approximate method : direct method, saves time and energy,
 1st step: Locate capacitors and replace them with an open circuit
 2nd step: Simplified circuit using Thevenin Theorem
 3rd step: Locate 2 main loops which;
 BEloop
 CE loop

22. VOLTAGE DIVIDER BIAS CIRCUIT
SimplifiedCircuit
Thevenin Theorem;
■ 2nd step: : Simplified circuit using Thevenin Theorem
2
1
2
1
2
1 //
R
R
R
R
R
R
RTH
+
×
=
=
CC
TH V
R
R
R
V
2
1
2
+
=
FromTheveninTheorem;

23. VOLTAGE DIVIDER BIAS CIRCUIT
 2nd step: Locate 2 main loops.
1
2
BE Loop CE Loop
1
2

24. VOLTAGE DIVIDER BIAS CIRCUIT
 BE Loop Analysis
■ From KVL;
Recall;
Substitutefor IE
0
TH B TH BE E E
V I R V I R
− + + + =
( 1) 0
( 1)
TH B TH BE B E
TH BE
B
RTH E
V I R V I R
V V
I
R R
β
β
− + + + + =
−
∴ =
+ +
B
E I
I )
1
( +
= β
1

25. VOLTAGE DIVIDER BIAS CIRCUIT
 CE Loop Analysis
■ From KVL;
■ Assume;
■ Therefore;
C
E I
I ≈
0
CC C C CE E E
V I R V I R
− + + + =
)
( E
C
C
CC
CE R
R
I
V
V +
−
=
∴
2

26. RTh: The voltage source is replaced by a short-circuit equivalent as shown in
Fig. 4.28.
RTh ⫽ R1储R2 (4.28)
ETh: The voltage source VCC is returned to the network and the open-circuit
Thévenin voltage of Fig. 4.29 determined as follows:
Applying the voltage-divider rule:
ETh ⫽ VR2
⫽ ᎏ
R
R
1
2
⫹
VC
R
C
2
ᎏ (4.29)
The Thévenin network is then redrawn as shown in Fig. 4.30, and IBQ can be de-
termined by first applying Kirchhoff’s voltage law in the clockwise direction for the
loop indicated:
ETh ⫺ IBRTh ⫺ VBE ⫺ IERE ⫽ 0
Substituting IE ⫽ (␤ ⫹ 1)IB and solving for IB yields
IB ⫽ ᎏ
RTh
E
⫹
Th
(
⫺
␤ ⫹
VB
1
E
)RE
ᎏ (4.30)
Although Eq. (4.30) initially appears different from those developed earlier, note
that the numerator is again a difference of two voltage levels and the denominator is
the base resistance plus the emitter resistor reflected by (␤ ⫹ 1)—certainly very sim-
ilar to Eq. (4.17).
Once IB is known, the remaining quantities of the network can be found in the
same manner as developed for the emitter-bias configuration. That is,
VCE ⫽ VCC ⫺ IC (RC ⫹ RE) (4.31)
which is exactly the same as Eq. (4.19). The remaining equations for VE, VC, and VB
are also the same as obtained for the emitter-bias configuration.
Determine the dc bias voltage VCE and the current IC for the voltage-divider config-
uration of Fig. 4.31.
159
4.5 Voltage-Divider Bias
EXAMPLE 4.7
Figure 4.28 Determining RTh.
R2
RTh
R1
Figure 4.29 Determining ETh.
R2
ETh
VR 2
VCC
+
–
+
–
R1
Figure 4.30 Inserting the
Thévenin equivalent circuit.
RE
ETh
IB
B
E
VBE
RTh
+
–
Figure 4.31 Beta-stabilized
circuit for Example 4.7.

27. Solution
Eq. (4.28): RTh ⫽ R1储R2
⫽ ᎏ
3
(3
9
9
k
k
⍀
⍀
⫹
)(3
3
.9
.9
k
k
⍀
⍀
)
ᎏ ⫽ 3.55 k⍀
Eq. (4.29): ETh ⫽ ᎏ
R
R
1
2
⫹
VC
R
C
2
ᎏ
⫽ ᎏ
3
(
9
3.
k
9
⍀
k⍀
⫹
)(
3
2
.
2
9
V
k⍀
)
ᎏ ⫽ 2 V
Eq. (4.30): IB ⫽ ᎏ
RTh
E
⫹
Th
(
⫺
␤ ⫹
VB
1
E
)RE
ᎏ
⫽ ⫽
⫽ 6.05 ␮A
IC ⫽ ␤IB
⫽ (140)(6.05 ␮A)
⫽ 0.85 mA
Eq. (4.31): VCE ⫽ VCC ⫺ IC (RC ⫹ RE)
⫽ 22 V ⫺ (0.85 mA)(10 k⍀ ⫹ 1.5 k⍀)
⫽ 22 V ⫺ 9.78 V
⫽ 12.22 V
Approximate Analysis
The input section of the voltage-divider configuration can be represented by the net-
work of Fig. 4.32. The resistance Ri is the equivalent resistance between base and
ground for the transistor with an emitter resistor RE. Recall from Section 4.4 [Eq.
(4.18)] that the reflected resistance between base and emitter is defined by Ri ⫽
(␤ ⫹ 1)RE. If Ri is much larger than the resistance R2, the current IB will be much
smaller than I2 (current always seeks the path of least resistance) and I2 will be ap-
proximately equal to I1. If we accept the approximation that IB is essentially zero am-
peres compared to I1 or I2, then I1 ⫽ I2 and R1 and R2 can be considered series ele-
1.3 V
ᎏᎏᎏ
3.55 k⍀ ⫹ 211.5 k⍀
2 V ⫺ 0.7 V
ᎏᎏᎏ
3.55 k⍀ ⫹ (141)(1.5 k⍀)
160 Chapter 4 DC Biasing—BJTs
Figure 4.32 Partial-bias circuit
for calculating the approximate
base voltage VB.

28. Approximate analysis:
2
2
2
2
( 1) 10
i R b
E E
R R I
R R
I
R R
β β
→
+ ⇒ >
 

If this condition applied then you can use approximation
method .
This makes IB to be negligible. Thus I1 through R1 is
almost same as the current I2 through R2.
Thus R1 and R2 can be considered as in series.
Voltage divider can be applied to find the voltage across
R2 ( VB)

29. ApproximateAnalysis
Then IB << I2 and I1 ≅ I2 :
When βRE > 10R2 ,
From Kirchhoff’s voltagelaw:
2
1
CC
2
B
R
R
V
R
V
+
=
E
E
E
R
V
I =
BE
B
E V
V
V −
=
E
E
C
C
CC
CE R
I
R
I
V
V −
−
=
)
R
(R
I
V
V
I
I
E
C
C
CC
CE
C
E
+
−
=
≅ This is a very stable bias
circuit. The currents and
voltages are nearly
independent of any
variations in β.

30. VB ⫽ ᎏ
R
R
1
2
⫹
VC
R
C
2
ᎏ (4.32)
Since Ri ⫽ (␤ ⫹ 1)RE ⬵ ␤RE the condition that will define whether the approxi-
mate approach can be applied will be the following:
␤RE ⱖ 10R2 (4.33)
In other words, if ␤ times the value of RE is at least 10 times the value of R2, the ap-
proximate approach can be applied with a high degree of accuracy.
Once VB is determined, the level of VE can be calculated from
VE ⫽ VB ⫺ VBE (4.34)
and the emitter current can be determined from
IE ⫽ ᎏ
V
R
E
E
ᎏ (4.35)
and ICQ
⬵ IE (4.36)
The collector-to-emitter voltage is determined by
VCE ⫽ VCC ⫺ ICRC ⫺ IERE
but since IE ⬵ IC,
VCEQ
⫽ VCC ⫺ IC (RC ⫹ RE) (4.37)
Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that ␤
does not appear and IB was not calculated. The Q-point (as determined by ICQ
and
VCEQ
) is therefore independent of the value of ␤.
Repeat the analysis of Fig. 4.31 using the approximate technique, and compare solu-
tions for ICQ
and VCEQ
.
Solution
Testing:
␤RE ⱖ 10R2
(140)(1.5 k⍀) ⱖ 10(3.9 k⍀)
210 k⍀ ⱖ 39 k⍀ (satisfied)
Eq. (4.32): VB ⫽ ᎏ
R
R
1
2
⫹
VC
R
C
2
ᎏ
⫽ ᎏ
3
(
9
3.
k
9
⍀
k⍀
⫹
)(
3
2
.
2
9
V
k⍀
)
ᎏ
⫽ 2 V
161
4.5 Voltage-Divider Bias
EXAMPLE 4.8

31. Note that the level of VB is the same as ETh determined in Example 4.7. Essen-
tially, therefore, the primary difference between the exact and approximate techniques
is the effect of RTh in the exact analysis that separates ETh and VB.
Eq. (4.34): VE ⫽ VB ⫺ VBE
⫽ 2 V ⫺ 0.7 V
⫽ 1.3 V
ICQ ⬵ IE ⫽ ᎏ
V
R
E
E
ᎏ ⫽ ᎏ
1
1
.5
.3
k
V
⍀
ᎏ ⫽ 0.867 mA
compared to 0.85 mA with the exact analysis. Finally,
VCEQ
⫽ VCC ⫺ IC(RC ⫹ RE)
⫽ 22 V ⫺ (0.867 mA)(10 kV ⫹ 1.5 k⍀)
⫽ 22 V ⫺ 9.97 V
⫽ 12.03 V
versus 12.22 V obtained in Example 4.7.
The results for ICQ
and VCEQ
are certainly close, and considering the actual vari-
ation in parameter values one can certainly be considered as accurate as the other.
The larger the level of Ri compared to R2, the closer the approximate to the exact so-
lution. Example 4.10 will compare solutions at a level well below the condition es-
tablished by Eq. (4.33).
Repeat the exact analysis of Example 4.7 if ␤ is reduced to 70, and compare solu-
tions for ICQ
and VCEQ
.
Solution
This example is not a comparison of exact versus approximate methods but a testing
of how much the Q-point will move if the level of ␤ is cut in half. RTh and ETh are
the same:
RTh ⫽ 3.55 k⍀, ETh ⫽ 2 V
IB ⫽ ᎏ
RTh
E
⫹
Th
(
⫺
␤ ⫹
VB
1
E
)RE
ᎏ
⫽ ⫽
⫽ 11.81 ␮A
ICQ
⫽ ␤IB
⫽ (70)(11.81 ␮A)
⫽ 0.83 mA
VCEQ
⫽ VCC ⫺ IC(RC ⫹ RE)
⫽ 22 V ⫺ (0.83 mA)(10 k⍀ ⫹ 1.5 k⍀)
⫽ 12.46 V
1.3 V
ᎏᎏᎏ
3.55 k⍀ ⫹ 106.5 k⍀
2 V ⫺ 0.7 V
ᎏᎏᎏ
3.55 k⍀ ⫹ (71)(1.5 k⍀)
162 Chapter 4 DC Biasing—BJTs
EXAMPLE 4.9

32. DC Bias with Voltage Feedback
Anotherway to
improvethe stability
of a bias circuitis to
add a feedbackpath
from collectorto
base.
In this bias circuit
the Q-pointis only
slightly dependenton
the transistorbeta, β.

33. Base-Emitter Loop
)
R
(R
R
V
V
I
E
C
B
BE
CC
B
+
β
+
−
=
From Kirchhoff’s voltagelaw:
CC C C B B BE E E
-V + I R +I R +V +I R 0
′ =
WhereIB << IC:
C
I
B
I
C
I
C
I' ≅
+
=
Knowing IC = βIB and IE ≅ IC, the loop
equationbecomes:
0
R
I
V
R
I
R
I
–
V E
B
BE
B
B
C
B
CC =
β
−
−
−
β
SolvingforIB:

34. Collector-Emitter Loop
Applying Kirchoff’s voltage law:
IE + VCE + I’CRC – VCC = 0
Since I′C ≅ IC and IC = βIB:
IC(RC + RE) + VCE – VCC =0
Solving for VCE:
VCE = VCC – IC(RC + RE)