the_wire

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TOPIC 4 – THE WIRE
Faizah Amir
EE603
CMOS IC DESIGN
Lesson Learning Outcome:
De To describe the impact of on-chip interconnect wire
the to the chip
To explain the interconnect parameters
To explain the electrical wire models
1
2
3

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Introduction
Impact of Interconnect Wire Parasitics:
1) An increase in propagation delay
- a drop in performance
2) Affect performance
- increase power dissipation
3) An introduction of extra noise sources
-affects the reliability of the circuit.
The Wire

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The Wire
The layout
The Cross-section
Classes of Parasitics
1) Capacitive
2) Resistive
3) Inductive
Wire model with most of the
wire parasitics
Wire model with only
capacitance

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Capacitance
Parallel Plate Capacitance Model of Interconnect Wire
The total capacitance of the
wire :
cint = εdi WL
tdi
W – the width of the wire
L – the length of the wire
tdi - the thickness of the dielectric
εdi – permittivity of the dielectric
Capacitance
Relative permittivity of some typical
dielectric material
Example :
Calculate the total capacitance of an
aluminium wire of 10cm long and 1µm wide
placed on 1µm thick SiO2 layer.
Ans :
ε= εo εr = 8.854x10-12F/m x 3.9
= 3.45 x 10-11 F/m
cint = 3.45 x 10-11 F/m x 1x10-6m x10x10-2m
1x10-6m
= 3.45 pF

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Fringing Capacitance
When the cross section of the wire (W x H) is made as large as
possible to minimize the resistance of the wire, fringing capacitance
should be taken into account in determining the total capacitance .
Fringing capacitance is the
capacitance between the side-walls
of the wire and the substrate.
H
Fringing versus Parallel Plate
From the plot:
For large values of (W/H), the
total capacitance approaches the
parallel-plate model.
For (W/H) smaller than 1.5, the
fringing component becomes
the dominant component.
Capacitance of interconnect wire as a function of (W/H)
(from [Schape83])

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Interwire Capacitance
Single Wire Capacitances
• Approximated by using a parallel-plate capacitance model.
• Fringing capacitance at conductor edges occur.
Parallel
Fringing
Interwire Capacitance
Multiple Wire Capacitances
• Multiple routing layers have capacitances to substrate and also have
capacitances among them (overlapping and side-wall).
• Capacitances can be very complex to calculate.

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Modern Interconnect
Multiple routing
layers of metal
Impact of Interwire Capacitance
Interconnect capacitance as a function of design rules. It consists of a
capacitance to ground and an inter-wire capacitance . (from [Schaper83])
From the graph:
• It is assumed that dielectric and wire
thickness are held constant while scaling
all other dimensions.
• As the design rule increased, the total
capacitance is increased, but the
interwire capacitance is decreased.

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Interwire Capacitance (0.25 µm CMOS)
Wire area and fringe capacitance values for typical 0.25 µm
CMOS process :
Top plate
of the
capacitor
The bottom plate
The area capacitances are expressed in aF/µm2, while the fringe capacitances
(given in the shaded rows) . (aF = attofarad = 1x10-18F)
Interwire Capacitance
Capacitance of Metal Wire
Example 1:
An aluminum wire of 10 cm long and 1 µm wide, routed on the first aluminum
layer. Compute the value of the total capacitance using the data presented in
table in the last slide.
Answer:
Area (parallel-plate) capacitance: = (L x W) x (parallel plate capacitance)
= (10cm x 1µm) x 30 aF/µm2
= 100,00 µm x 1 µm x 30 aF/µm2 = 3 pF
Fringing capacitance = 2 x (100,00 µm x 1µm) x 40 aF/µm2 = 8 pF
(the factor 2 in the computation of the fringing capacitance
because of two sides of the wire ).
Total capacitance = 3pF + 8pF = 11 pF

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Interwire Capacitance
Capacitance of Metal Wire
Example 2:
Suppose now that a second wire is routed alongside the first one, separated by
only the minimum allowed distance. From Table Interwire capacitance for
different interconnect layers below, determine the interwire capacitance.
Answer :
Cinter = (100,00 µm x 1 µm ) x 95 aF/ µm2 = 9.5 pF
Wire Resistance
The resistance of a wire is proportional to
its length L and inversely proportional to
its cross-section A.
where the constant ρ is the resistivity of the
material (in Ω-m).

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Wire Resistance
Resistivity of commonly-used conductors
(at 20° C).
Sheet Resistance
Another expression of wire resistance:
where
R is the sheet resistance of the material, having units of Ω/
(pronounced as Ohm-persquare).

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Sheet Resistance
From the table, can you explain why aluminum is the preferred material
for the wiring of long interconnections and polysilicon should only be
used for local interconnect?
Sheet Resistance
H
L
H
L
L L
L
L

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Resistance of a Metal Wire
Example 1:
Consider the aluminum wire with is 10 cm long and 1 µm wide, and
is routed on the first aluminum layer. Assuming a sheet resistance for Al1 of
0.075 Ω/ . Calculate the total resistance of the wire.
Ans:
Rwire =
= 0.075 Ω/ x (100,000 µm) / (1 µ m) = 7.5 kΩ
Interwire Inductance
By definition, the state that a changing current
passing through an inductor generates a voltage
drop ∆V.
Inductance becomes an issue when
the switching frequency range is
bigger than GHz.

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Interwire Inductance
• It is possible to compute the inductance a wire
directly from its geometry and its environment.
• A simpler approach relies on the fact that the
capacitance C and the inductance L (per unit length)
of a wire are related by the following expression:
CL = εµ
Where :
ε - permittivity of the surrounding dielectric
µ - permeability of the surrounding dielectric
Interwire Inductance
Example:
Consider an Al1 wire implemented in the 0.25 micron CMOS technology and
routed on top of the field oxide (SiO2). Calculate the inductance of the
aluminium wire of 0.4µm width.
(Given permeability of free space, µ0 = 4π x 10-7 H/m and relative
permeability of SiO2 , µr = 1).
Answer :
CL = εµ
L = εµ /C
= (εo x εr) (µ0 x µr) / [ (W x3.9) + 2(Wx40)]
= (3.9 x 8.854 x 10-11F/m) (1x 4π x 10-7 H/m)
( 0.4µm x 30 aF/µm) + 2 ( 0.4µm x 4 aF/µm)
= 0.985 pF/µm

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Wire Models
• Electrical wire model is used to estimate and
approximate the real behaviour of the wire as a
function of its parameters.
• These models vary from very simple to very
complex depending upon the effects that are
being studied and the required accuracy.
Wire Models
Examples of wire model:
a. Ideal wire
b. Lumped model
c. Lumped RC model
d. Distributed RC model

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Ideal Wire Models
In Ideal Wire Model, it assumed that :
• no attached parameters or parasitics.
• no impact on the electrical behavior of the circuit.
• the wire is viewed as an equipotential region: same voltage is
present at every segment at every point in time
• simplistic but valuable model for:
early design phases (to concentrate on transistors behaviour)
evaluating a single gate (wires are very short, parasitics can
be ignored)
Lumped Model
• In a real wire, parasitics are distributed along the
length.
• The lumped model may be useful when:
a single parasitic component is dominant
or
the interaction between the components is small
or
looking at only one aspect of the circuit behaviour

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The Lumped Model
Example (the lumped capacitance model):
If : Resistive and Inductive components are small and
Switching frequencies are in the low to medium range
Then :
It is meaningful to consider only the capacitive component
and
To lump the distributed capacitance into a single capacitor
The Lumped RC Model
• The Lumped-Capacitor model is unrealistic. (The resistance of
metal wires of a few millimeters cannot be ignored)
• On the other hand, the distributed RC model is complex. (No
close-form solutions exist!)
• The Lumped RC model is an alternative for moderately long wires.
(But too pessimistic for long wires!)
• Its solution is similar to the lumped capacitance model solution.

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Distributed RC Model
• As mentioned before, the distributed RC model is complex and
the calculation involve a set of partial differential equations.
• The distributed RC Model can be approximated by a lumped RC
ladder network, which can be easily used in computer-aided
analysis.
Distributed RC model
Schematic symbol for distributed RC model

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Good Luck !!!