This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
2. 2
Agenda
General Overview of UVM
Challenges in using UVM at SoC level
Proposal for using UVM at SoC level
3. What is UVM?
Universal Verification Methodology
Testbenches for HDL designs
UVM has SystemVerilog Base Class Library
Based on constrained Random Verification approach
Industry standard developed by Accellera
Apache 2.0 open-source license
Key features of the methodology:
Data design and stimulus generation
Building and running a verification environment
3C : Checker, Coverage and Constrains
3
4. 4
The Goal : Automation
Source: Accellera DAC Presentation
5. 5
Key Features of UVM [1]
Built-in automation
Transaction manipulation (Print / Pack / [Deep] Copy / Record)
Defined testbench build and hook-up mechanism
Flexible automatic test phase interface
Lot of phases defined for synchronization
Powerful stimulus generation mechanism using sequences
On-the-fly randomization control
Sequence Layering & nested sequence
Virtual sequences [Controlling multiple sequencers from ‘central place’]
TLM communication
Modular and Language independent
Supports reuse
Module-to-system
Project-to-project
6. 6
Key Features of UVM [2]
Sequences or Testcases
UVM Tests or sequences separated from TestBench environment
Uniformity
Standard structure for all Testbench components
UVM factories
UVM factories give flexibility
Easy to update or modify components without changing original code
Configuration
UVM configuration helps in customizing the environment from Top or anywhere
And more…
Messaging utilities with on-the-fly control over verbosity
Ensures random stability
Compile once and run many times using snapshot
7. 77
Env
(UVC)Agent
Agent
7
Reusable UVM Component Architecture
Agent
Sequencer
sequences
tlm i/f
Driver
vif
tlm i/f
Config:
active_passive
• Generates sequences of
transactions
and passes them to the driver
• Connected to the driver via
TLM interface
• Pulls items from the
sequencer
• Implements signal-level
protocol
and sends to the DUT
• Virtual Interface –
Connection
from the testbench to the
DUT
• Contains DUT signals for a
device
DUT
Monitor
Coverage
Checking
vif
tlm i/f
APB IF
• Independently collects
transactions
from the DUT interface
• Contains events, status,
checking
and coverage
• Sends transactions to a
scoreboard
via TLM write port
• SystemVerilog Interface
• Contains DUT bus signals
• Encapsulates the
components for
a device on the bus
• Contains shared config
information
• A bus protocol can have a
variable number of devices
• Each is represented as an agent
• An env encapsulates and
configures multiple agents
• Also referred to as an UVM
Verification Component (UVC)
8. 88
What Are the Benefits Of This
Architecture?
UVC (UVM Verification Component)
Master Agent
Sequencer
sequences
tlm i/f
Driver
vif
tlm i/f
Collector
vif
tlm i/f
Config:
Slave Agent
Sequencer
sequences
tlm i/f
Driver
vif
tlm i/f
DUT
APB IF
Passive
Architecture exactly the
same across all languages!
Encapsulating components makes
it modular and simplifies maintenance
“Virtual” sequences enable
control at the system level
Control and configure
from above Easy-to-use test
writer interface
Supports module-
to-system reuseConfig:
active
Each component has an UVM parent class
with built-in utilities and automation …
Monitor
tlm i/f
tlm i/f
Collector
vif
tlm i/f
Monitor
tlm i/f
tlm i/f
Config:
Config:
passive
9. 9
Agenda
General Overview of UVM
Challenges in using UVM at SoC level
Proposal for using UVM at SoC level
10. 10
Quick setup of SoC verification env (integration of
all verification component)
Synchronization or Control of verification
components
More emphasize is on system scenarios/
integration rather than on randomization
Should able to reuse configuration of IP from IP
or sub-system testcases
Should able to re-produce validation issues
Challenges for SoC verification
11. Reference IP
UVM Verification Flow User Code
TLM Platform
IO Injector
Receiver
Reference
IP
Verification
SoC
Integration
SoC Validation
ICN
Memory
Virtual Register
I/O UVC
Sequencer
TLM
Driver
Monitor
Seqs
Seqs
Seqs
ICN UVC
Sequencer
TLM
Driver
Monitor
Seqs
Seqs
Seqs
Virtual
Sequence
RTL IP
Reference IP
Protocol
Driver
Protocol
Driver
Monitor
TLM Port
Monitor
TLM Port
12. RTL IP
UVM Verification Flow at SoC level User Code
TLM Platform
IO Injector
Receiver
Reference
IP
Verification
SoC
Integration
SoC Validation
ICN
Memory
Virtual Register
I/O UVC
Sequencer
DriverMonitor
Seqs
Seqs
Seqs
ICN UVC
Sequencer
DriverMonitor
Seqs
Seqs
Seqs
Processor
No Simple way to control UVC from C
13. 13
Challenges in using UVM at SoC level
No good way to control UVC from C or processor
No standard way to support multiple language
(available from Cadence but not Accellera or
IEEE standard)
Easier said than done to reuse the test cases
(sequences) from IP->sub-system->SoC.
14. Proposed UVC Architecture… User Code
TLM Platform
IO Injector
Receiver
Reference
IP
Verification
SoC
Integration
SoC Validation
I/O UVC
Sequencer
TLM
Driver
Monitor
Seqs
Seqs
Seqs
TLM 2.0 Export
Processor Controlled Seq
Reg
Reg
RegSequence Name Reg
Control Reg
15. 15
Work done
Developed a wrapper to connect TLM port
between SystemC and UVM
Added TLM export in sequencer
Added a sequence with registers which can be
controlled through TLM port
Developed Test platform to demonstrate
controlling of sequence from TLM IP
16. RTL IP3
SoC Verification with UVM User Code
TLM Platform
IO Injector
Receiver
Reference
IP
Verification
SoC
Integration
SoC Validation
ICNTLM Channel
EMI
Test Code (in C)
Transactor
USB
Ether
net
TLM RTL User Code Transactor (Sc or SCEMI)
UVC
IO
Injector
Receiver
SOC
LMI
SLM
USB
Ethernet
ISS
BFM
UVC
UVC
PCI
Tx/Rx Frame
17. 17
Workdone
Connection of EMI interface with SystemC TLM
channel
Connection of TLM SystemC port with UVM port
Developed Test Platform to demonstrate
controlling of sequence from Processor
C code running on ISS, which is writing to a TLM
Port about the sequence information
Based on the received information, UVC
sequence runs the required sequence or
generate the random/directed traffic
Checked the generated data through C testcase
18. 18
UVM good at IP level and best with standard
interfaces like AHB, AXI etc
Best for constraint randomization verification
Good in reusing verification components (like
driver, monitor or agents)
For efficient reuse verification engineers need to
be expert in UVM and OOPs concept
Still some gray areas for how to use UVM at SoC
and Accellera can work in this area
My view….
19. 19
Wishlist for UVM 2.0
Seamless connection between UVM and SystemC ports
TLM export in sequencer library
Sequence with registers which can be written from TLM
port in sequencer
Event queue in sequencer for synchronization
Standard name for some of the sequences like
generate_interrupt, clear_interrupt, dma_data_transfer
etc