Addition and Subtraction – Multiplication – Division – Floating Point Representation – Floating Point Addition and Subtraction

1. Velammal Engineering College
Department of Computer Science
and Engineering
Welcome…
Ms. R. Amirthavalli,
Asst. Prof,
CSE,
Velammal Engineering College
Slide Sources: Patterson &
Hennessy COD book
website (copyright Morgan
Kaufmann) adapted and
supplemented

2. Subject Code / Name:
19IT202T /
Computer Architecture

3. Syllabus – Unit II
UNIT-II ARITHMETIC FOR COMPUTERS
Addition and Subtraction – Multiplication – Division – Floating
Point Representation – Floating Point Addition and Subtraction.

4. Text Books
• Book 1:
o Name: Computer Organization and Design: The
Hardware/Software Interface
o Authors: David A. Patterson and John L. Hennessy
o Publisher: Morgan Kaufmann / Elsevier
o Edition: Fifth Edition, 2014
• Book 2:
o Name: Computer Organization and Embedded Systems
Interface
o Authors: Carl Hamacher, Zvonko Vranesic, Safwat Zaky and
Naraig Manjikian
o Publisher: Tata McGraw Hill
o Edition: Sixth Edition, 2012

5. • numbers may be represented in any base
• Computer - base 2 numbers are called binary numbers
• A single digit of a binary number is the “atom” of computing,
since all information is composed of binary digits or bit.
• Alternatives: high or low, on or off , true or false, or 1 or 0
• Least Significant Bit(LSB): The rightmost bit in a MIPS word.
• Most Significant Bit(MSB): The left most bit in a MIPS word.
Numbers

6. The Binary Number System
• Name
o “binarius” (Latin) => two
• Characteristics
o Two symbols
• 0 1
o Positional
• 1010B ≠ 1100B
• Most (digital) computers use the binary number
system Terminology
• •Bit: a binary digit
• •Byte: (typically) 8 bits

7. Number Representation
• Three systems:
o Sign-and-magnitude
o 1’s complement
o 2’s complement
• In all three systems, the leftmost bit is 0 for positive
numbers and 1 for negative numbers.
• Positive values have identical representations in all
systems.
• Negative values have different representations.
• Ex: 10112

8. • Sign Magnitude: One's Complement Two's Complement
000 = 0 000 = 0 000 = 0
001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = 0 100 = -3 100 = -4
101 = -1 101 = -2 101 = -3
110 = -2 110 = -1 110 = -2
111 = -3 111 = 0 111 = -1
• Issues:
o balance – equal number of negatives and positives
o ambiguous zero – whether more than one zero representation
o ease of arithmetic operations
• Which representation is best? Can we get both balance and non-ambiguous zero?
Possible Representations
ambiguous
zero
ambiguous
zero

9. Signed Magnitude
• In this notation, an extra bit is added to the left of the
number to notate its sign.
• 0 indicates +ve and 1 indicates -ve.
• Using 8 bits,
• +13 is 00001101 and +11 is 00001011.
• -13 is 10001101 and -11 is 10001011.

10. 1's Complement
• In this notation positive numbers are represented exactly
as regular binary numbers.
• Negative numbers are represented simply by flipping the
bit, i.e. 0's become 1 and 1's become 0.
• So 13 will be 00001101 and 11 will be 00001011.
• -13 will be 11110010 and -11 will be 11110100.

11. 2's Complement
• In this method a negative number is notated by first
determining the 1's complement of the positive number
and then adding 1 to it.
• So 8-bit -13 will be 11110010
• (1's complement) + 1 = 11110011;
• -11 will be 11110101.

12. Question
• Find the 2’s-complement of 1011010?
• 0100110

13. • 32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten
...
0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...
1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
MIPS – 2’s complement
maxint
minint
Negative integers are exactly those that have leftmost bit 1

14. • Sign Extension Shortcut: To convert an n-bit integer into an
integer with more than n bits – i.e., to make a narrow integer fill
a wider word – replicate the most significant bit (msb) of the
original number to fill the new bits to its left
o Example: 4-bit 8-bit
0010 = 0000 0010
1010 = 1111 1010
o why is this correct? Prove!
Two's Complement
Operations

15. Binary Addition

16. Binary Addition
• 710 + 610
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610

17. Binary Addition
• 710 + 610
0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710
0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610
1 2

18. Binary Addition
• 710 + 610
1
0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710
0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610
12
0

19. Binary Addition
• 710 + 610
1
0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710
0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610
012
1
1

20. Binary Addition
• 710 + 610
1 1
0000 0000 0000 0000 0000 0000 0000 0 1112 = 710
0000 0000 0000 0000 0000 0000 0000 0 1102 = 610
1012
1

21. Binary Addition
• 710 + 610
11
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610
0000 0000 0000 0000 0000 0000 0000 11012

22. Binary Addition
• 710 + 610
11
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610
0000 0000 0000 0000 0000 0000 0000 11012 = 1310

23. Binary Subtraction

24. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610

25. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 011 1 2 = 710
0000 0000 0000 0000 0000 0000 0000 011 0 2 = 610
1

26. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 01 1 12 = 710
0000 0000 0000 0000 0000 0000 0000 01 1 02 = 610
1
0

27. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 0 1 112 = 710
0000 0000 0000 0000 0000 0000 0000 0 1 102 = 610
0 01

28. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610
0000 0000 0000 0000 0000 0000 0000 00012

29. Binary Subtraction
• Direct Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 01112 = 710
0000 0000 0000 0000 0000 0000 0000 01102 = 610
0000 0000 0000 0000 0000 0000 0000 00012 = 110

30. Binary Subtraction
• 2’s Complement Method
710 - 610
0000 0000 0000 0000 0000 0000 0000 01112 = 710
2’s c of - 610=1111 1111 1111 1111 1111 1111 1111 10102 = 610
0000 0000 0000 0000 0000 0000 0000 00012 = 110

31. Overflow
• When the actual result of an arithmetic operation is
outside the representable range, an arithmetic
overflow has occurred.
• No overflow when adding a positive and a negative
number
• No overflow when subtracting numbers with the same
sign
• Overflow occurs when adding two positive numbers
produces a negative result, or when adding two
negative numbers produces a positive result.

32. Overflow

33. Overflow - Example
• No overflow when adding a positive and a negative
number
• A+B
• A = +3
• B = -2
+3 => 011
-2 => 110
• -----------
+1 => 001
• Result - representable range
n=3 bits => Range: - 4 to +3
+3 011
+2 010
+1 001
0 000
-1 111
-2 110
-3 101
-4 100

34. Overflow - Example
• No overflow when subtracting numbers with the same
sign
• A - B
• A = - 3
• B = - 2
• (-3) – (-2) => -3 + 2
-3 => 101
+2 => 010
• -----------
-1 => 111
• Result - representable range
n=3 bits => Range: - 4 to +3
+3 011
+2 010
+1 001
0 000
-1 111
-2 110
-3 101
-4 100

35. Overflow - Example
• Overflow occurs when adding two positive numbers
produces a negative result, or when adding two
negative numbers produces a positive result.
• A + B
• A = + 3
• B = + 3
+3 => 011
+3 => 011
• -----------
-2 => 110
n=3 bits => Range: - 4 to +3
+3 011
+2 010
+1 001
0 000
-1 111
-2 110
-3 101
-4 100

36. • No overflow when adding a positive and a negative number
• No overflow when subtracting numbers with the same sign
• Overflow occurs when the result has “wrong” sign (verify!):
Operation Operand A Operand B Result
Indicating Overflow
A + B  0  0  0
A + B  0  0  0
A – B  0  0  0
A – B  0  0  0
• Consider the operations A + B, and A – B
o can overflow occur if B is 0 ?
o can overflow occur if A is 0 ?
Detecting Overflow

37. Multiply
• Grade school shift-add method:
Multiplicand 1000
Multiplier 1001
x 1000
0000
0000
1000
Product 01001000
• m bits x n bits = m+n bit product
• Binary makes it easy:
o multiplier bit 1 => copy multiplicand (1 x multiplicand)
o multiplier bit 0 => place 0 (0 x multiplicand)
x

38. Shift-add Multiplier
64-bit ALU
Control test
Multiplier
Shift right
Product
Write
Multiplicand
Shift left
64 bits
64 bits
32 bits
Done
1. Test
Multiplier0
1a. Add multiplicand to product and
place the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0
Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
Multiplicand register, product register, ALU are
64-bit wide; multiplier register is 32-bit wide
Algorithm
32-bit multiplicand starts at right half of multiplicand register
Product register is initialized at 0

39. Shift-add Multiplier
Itera Step Multiplier Multiplicand Product
-tion
0 init 0011 0000 0010 0000 0000
values
1 1a 0011 0000 0010 0000 0010
2 0011 0000 0100 0000 0010
3 0001 0000 0100 0000 0010
2 1a 0001 0000 0100 0000 0110
2 0001 0000 1000 0000 0110
3 0000 0000 1000 0000 0110
3 1 0000 0000 1000 0000 0110
2 0000 0001 0000 0000 0110
3 0000 0001 0000 0000 0110
4 1 0000 0001 0000 0000 0110
2 0000 0010 0000 0000 0110
3 0000 0010 0000 0000 0110
Example: 0010 * 0011:
Algorithm
Done
1. Test
Multiplier0
1a. Add multiplicand to product and
place the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0
Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
Final Product

40. Signed Multiplication
Booth Algorithm
The Booth Algorithm:
• The Booth algorithm generates a 2n-bit product
and treats both positive and
• negative 2’scomplement n-bit operands
uniformly.
• The Booth algorithm has two attractive features.
First, it handles both positive and negative multipliers
uniformly.
Second, it achieves some efficiency in the number of
additions required when the multiplier has a few large blocks of
1s.

41. Signed Multiplication
Booth Algorithm
Booth multiplier recoding table

42. Booth Algorithm
Booth Recoded Multipliers
Ex:
-6 in 2’s complement is 11010
11010 0
Peform recoding
1 1 0 1 0 0
Add a zero to
the RHS of the
multiplier
0
-1
+1
-1
So this is the
recoded multiplier
0

43. Booth Multiplication
• Let us perform +13 * -6
Steps:
• Recode the multiplier
-6 when recoded is 0 -1 +1 -1 0
+13 = 0 1 1 0 1
- 6 = 0-1+1-10
Note:
Multiplier bit is :
0 All 0s
+1 multiplicand
-1 2’s c of multiplicand
0 1 1 0 1
X 0-1+1-10
0 0 0 0 0
1 0 0 1 1
0 1 1 0 1
1 0 0 1 1
0 0 0 0 0
1 1 1 1 0 1 1 0 0 1 0
0 0 0 0 0
1 1 1 1
0 0 0
1 1
0
Final Product = 11101100102 = -7810
Carry is ignored

44. 1001 Quotient
Divisor 1000 1001010 Dividend
–1000
10
101
1010
-1000
10 Remainder
• Junior school method: see how big a multiple of the divisor can be
subtracted, creating quotient digit at each step
• Binary makes it easy  first, try 1 * divisor; if too big, 0 * divisor
• Dividend = (Quotient * Divisor) + Remainder
Division

45. Restoring Division
64-bit ALU
Control
test
Quotient
Shift left
Remainder
Write
Divisor
Shift right
64 bits
64 bits
32 bits
Done
Test Remainder
2a. Shift the Quotient register to the left,
setting the new rightmost bit to 1
3. Shift the Divisor register right 1 bit
33rd repetition?
Start
Remainder < 0
No: < 33 repetitions
Yes: 33 repetitions
2b. Restore the original value by adding
the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0
1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Remainder > 0
–
Divisor register, remainder register, ALU are
64-bit wide; quotient register is 32-bit wide
Algorithm
32-bit divisor starts at left half of divisor register
Remainder register is initialized with the dividend at right
Why 33? We shall see later…
Quotient register is
initialized to be 0

46. Division
Done
Test Remainder
2a. Shift the Quotient register to the left,
setting the new rightmost bit to 1
3. Shift the Divisor register right 1 bit
33rd repetition?
Start
Remainder < 0
No: < 33 repetitions
Yes: 33 repetitions
2b. Restore the original value by adding
the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0
1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Remainder > 0
–
Itera- Step Quotient Divisor Remainder
tion
0 init 0000 0010 0000 0000 0111
1 1 0000 0010 0000 1110 0111
2b 0000 0010 0000 0000 0111
3 0000 0001 0000 0000 0111
2 1 0000 0001 0000 1111 0111
2b 0000 0001 0000 0000 0111
3 0000 0000 1000 0000 0111
3 1 0000 0000 1000 1111 1111
2b 0000 0000 1000 0000 0111
3 0000 0000 0100 0000 0111
4 1 0000 0000 0100 0000 0011
2a 0001 0000 0100 0000 0011
3 0001 0000 0010 0000 0011
5 1 0001 0000 0010 0000 0001
2a 0011 0000 0010 0000 0001
3 0011 0000 0001 0000 0001
Example: 0111 / 0010:
Algorithm
R = Reminder – Divisor
R = 0000 0111 – 0010 0000
R = 1110 0111
Restore,
R = R + D
R = Reminder – Divisor
R = 0000 0111 – 0001 0000
R = 1111 0111
Restore,
R = R + D
R = Reminder – Divisor
R = 0000 0111 – 0000 1000
R = 1111 1111
Restore,
R = R + D
R = Reminder – Divisor
R = 0000 0111 – 0000 0100
R = 0000 0011
R = Reminder – Divisor
R = 0000 0011 – 0000 0010
R = 0000 0001

47. Floating Point
• We need a way to represent
o numbers with fractions, e.g., 3.1416
o very small numbers (in absolute value), e.g.,
.00000000023
o very large numbers (in absolute value) , e.g., –
3.15576 * 1046

48. Floating Point
• Still use a fixed number of bits
o Sign bit S, exponent E, significand F
o Value: (-1)S x (1+F) x 2E
• IEEE 754 standard
4
8
Size Exponent Significand Range
Single precision 32b 8b 23b 2x10+/-38
Double precision 64b 11b 52b 2x10+/-308
S E F

49. IEEE 754 Floating-point
Standard
• IEEE 754 floating point standard:
o single precision: one word
o double precision: two words
31
sign
bits 30 to 23
8-bit exponent
bits 22 to 0
23-bit significand
31
sign
bits 30 to 20
11-bit exponent
bits 19 to 0
upper 20 bits of 52-bit significand
bits 31 to 0
lower 32 bits of 52-bit significand

50. Floating Point Exponent
• Exponent specified in biased or excess
notation
• Why?
o To simplify sorting
o Sign bit is MSB to ease sorting
o 2’s complement exponent:
• Large numbers have positive exponent
• Small numbers have negative exponent
o Sorting does not follow naturally
5
0

51. Excess or Biased
Exponent
• Value: (-1)S x (1 + F) x 2(E-bias)
o SP: bias is 127
o DP: bias is 1023
5
1
Exponent 2’s Compl Excess-127
-127 1000 0001 0000 0000
-126 1000 0010 0000 0001
… … …
+127 0111 1111 1111 1110

52. Floating Point
Normalization
• S,E,F representation allows more than one
representation for a particular value, e.g.
1.0 x 105 = 0.1 x 106 = 10.0 x 104
o This makes comparison operations difficult
o Prefer to have a single representation
• Hence, normalize by convention:
o Only one digit to the left of the floating point
o In binary, that digit must be a 1
• Since leading ‘1’ is implicit, no need to store it
• Hence, obtain one extra bit of precision for free
5
2

53. FP Overflow/Underflow
• FP Overflow
o Analogous to integer overflow
o Result is too big to represent
o Means exponent is too big
• FP Underflow
o Result is too small to represent
o Means exponent is too small (too negative)
• Both can raise an exception under IEEE754
5
3

54. IEEE754 Special Cases
5
4
Single Precision Double Precision Value
Exponent Significand Exponent Significand
0 0 0 0 0
0 nonzero 0 nonzero denormalized
1-254 anything 1-2046 anything fp number
255 0 2047 0 infinity
255 nonzero 2047 nonzero
NaN (Not a
Number)

55. Show the IEEE 754 binary
representation of the number -0.75ten in
single and double precision
Converting -0.75ten to binary
0.75 x 2 = 1.50 (take only integral part, ie 1)
0.50 x 2 = 1.00
0.11 x 2 -0
After Normalizing the above value is 1.1 x 2 -1
The general representation for a single precision no is
(-1)S x (1 + F) x 2(E-127)
Subtracting the bias 127 from the exponent of
-1.1two x 2-1 yields
(-1)1 x (1+.1000 0000 0000 0000 0000 000two) x 2(126-127)
(Contd…)

56. (Contd…)
The single precision binary representation of -0.75ten is
then
The double precision representation is
Show the IEEE 754 binary
representation of the number -0.75ten in
single and double precision