Design Robustness Evaluation for Permanent and Single Event Transient
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Design Automation Conference (DAC) - 2016 Austin, TX - USA Richard Newton Fellow Program - Poster Session
![NFAS-tool: Design Robustness Evaluation for Permanent and Single
Event Transient Faults in Combinational Logic Cells
Universidade Federal do Rio Grande do Sul
Instituto de Informática
Av. Bento Gonçalves, 9500 - Campus do Vale. Bloco IV
CP15064, 91501-970- Porto Alegre-Brazil
{yqaguiar, alzimpeck, cmeinhardt, reis}@inf.ufrgs.br
Ygor Q. De Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da L. Reis
Fault Injection
In the nanoscale technology context, to design reliable systems out of unreliable devices, it is imperative to do fault modeling and the
adoption of EDA tools, which allow the assessment of circuits regarding the reliability [1]. Thus, this work presents a tool to evaluate the
design robustness of logic circuits under three different and main types of faults found in combinational cells at nanotechnologies: Single
Event Transient, Stuck-On and Stuck-Open faults.
SET
Stuck-Open (SOF)Stuck-On (SOnF)Single Event Transient (SET)
A B OUT OUT*
0 0 1 X
0 1 0 0
1 0 0 0
1 1 0 0
Connection between two nodes of the
transistor will never happen.
Connection between two nodes of the
transistor always happen.
Single particle hits on a sensitive region of transistor
and generates a transient pulse [2].
A B OUT OUT*
0 0 1 1
0 1 0 Z
1 0 0 0
1 1 0 0
1) Output floats in a high
impedance state.
2) Maintain the voltage of
the previous state.
1) Output generates an
unpredictable result.
2) Short-circuit: Pull-up and
pull-down conducting together.
Independently of the signal applied at the gate terminal.Pulse can be captured by a memory element (bit flip).
Nanotechnology Fault Analysis Simulation Tool (NFAS-tool)
REFERENCES
[1] ANGHEL L. and NICOLAIDIS, M. "Defects tolerant logic gates for unreliable future nanotechnologies."
In Computational and Ambient Intelligence, pp. 422-429. Springer Berlin Heidelberg, 2007.
[2] MESSENGER, “Collection of Charge on Junction Nodes from Ion Tracks”. IEEE Trans. of Nuclear Science,
1982.
NFAS-tool evaluates the behavior of combinational cells under faults.
JAVA programming language
NGSpice Electrical Simulator
Analysis in terms of:
Clock Frequency
Technology Nodes
Holding Time
LET (Linear Energy Transfer)
Fault propagation through a chain of inverters
Chain of Inverters
Response Analysis
FURG](https://image.slidesharecdn.com/dac2016ygor2-160816225915/85/Design-Robustness-Evaluation-for-Permanent-and-Single-Event-Transient-1-320.jpg)
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Design Robustness Evaluation for Permanent and Single Event Transient
- 1. NFAS-tool: Design Robustness Evaluation for Permanent and Single Event Transient Faults in Combinational Logic Cells Universidade Federal do Rio Grande do Sul Instituto de Informática Av. Bento Gonçalves, 9500 - Campus do Vale. Bloco IV CP15064, 91501-970- Porto Alegre-Brazil {yqaguiar, alzimpeck, cmeinhardt, reis}@inf.ufrgs.br Ygor Q. De Aguiar, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da L. Reis Fault Injection In the nanoscale technology context, to design reliable systems out of unreliable devices, it is imperative to do fault modeling and the adoption of EDA tools, which allow the assessment of circuits regarding the reliability [1]. Thus, this work presents a tool to evaluate the design robustness of logic circuits under three different and main types of faults found in combinational cells at nanotechnologies: Single Event Transient, Stuck-On and Stuck-Open faults. SET Stuck-Open (SOF)Stuck-On (SOnF)Single Event Transient (SET) A B OUT OUT* 0 0 1 X 0 1 0 0 1 0 0 0 1 1 0 0 Connection between two nodes of the transistor will never happen. Connection between two nodes of the transistor always happen. Single particle hits on a sensitive region of transistor and generates a transient pulse [2]. A B OUT OUT* 0 0 1 1 0 1 0 Z 1 0 0 0 1 1 0 0 1) Output floats in a high impedance state. 2) Maintain the voltage of the previous state. 1) Output generates an unpredictable result. 2) Short-circuit: Pull-up and pull-down conducting together. Independently of the signal applied at the gate terminal.Pulse can be captured by a memory element (bit flip). Nanotechnology Fault Analysis Simulation Tool (NFAS-tool) REFERENCES [1] ANGHEL L. and NICOLAIDIS, M. "Defects tolerant logic gates for unreliable future nanotechnologies." In Computational and Ambient Intelligence, pp. 422-429. Springer Berlin Heidelberg, 2007. [2] MESSENGER, “Collection of Charge on Junction Nodes from Ion Tracks”. IEEE Trans. of Nuclear Science, 1982. NFAS-tool evaluates the behavior of combinational cells under faults. JAVA programming language NGSpice Electrical Simulator Analysis in terms of: Clock Frequency Technology Nodes Holding Time LET (Linear Energy Transfer) Fault propagation through a chain of inverters Chain of Inverters Response Analysis FURG