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PLD 
THIẾT BỊ LOGIC LẬP TRÌNH ĐƯỢC 
(Programmable Logic Device) 
NguyenTrongLuat 
1
BOÄ NHÔÙ BAÙN 
DAÃN 
Boä nhôù baùn daãn 
Boä nhôù baûng Boä nhôù haøm 
RAM ROM 
tónh ñoäng MROM 
PROM 
EPROM 
EEPRO 
M 
PLD 
PLAPALLCA 
PPA 
LEPLPA 
LEEPPAL 
EPL 
D 
PEELGAL 
NguyenTrongLuat 
2
BOÄ NHÔÙ ROM 
Input: caùc tín hieäu ñòa chæ (Address) 
Output: caùc tín hieäu döõ lieäu (Data) 
A0 
A1 
An-1 
D0 
D1 
Dm-1 
INPUT 
(n ñöôøng) 
OUTPUT 
(m ñöôøng) 
Kích thöôùc ROM: 2n x m (bit) 
NguyenTrongLuat 
3
word line 
bit 
line 
101 
1 
0 
1 
1 
1 
1 
1 
0 
1 
1 
1 
Baûng naïp ROM 
A2 A1 
0 
1 
0 
0 
A0 
D3 D2 D1 
0 0 D0 
0 
0 0 
1 
0 1 
0 
0 1 
1 
1 0 
0 
1 0 
1 
1 1 
0 
1 1 
1 
1 1 1 
0 1 1 0 
1 1 0 1 
1 0 1 1 
1 0 0 0 
1 0 0 1 
0 0 1 0 
0 1 0 0 
0 
Caáu truùc noäi ROM 8 x 
4 (bit) 
1 
NguyenTrongLuat 
4
ROM 128 x 1 (bit) giaûi maõ 
2 chieàu 
NguyenTrongLuat 
5
ROM 32K x 8 (bit) = 32KB 
NguyenTrongLuat 
6
Caáu truùc ROM coù ngoõ vaøo 
ñieàu khieån 
NguyenTrongLuat 
7
Coång ñeäm ba traïng thaùi (Tristate Output 
Buffer): 
3 traïng thaùi (tristate): LOW / HIGH / HIGH impedance 
Traïng thaùi toång trôû cao (HIGH impedance): ngoõ ra hôû maïch 
- Ngoõ ñieàu khieån 3 traïng thaùi: 
* HIGH: The buffer is Active 
* LOW: HIGH 
impedance 
NguyenTrongLuat 
8
Caùc EPROM thoâng duïng 
NguyenTrongLuat 
9
PLA 
(PROGRAMMABLE LOGIC 
ARRAY) 
INPUT 
(n bit) 
OUTPUT 
(m bit) 
k product term (soá 
haïng tích) 
Daõy 
AND 
Daõy 
OR 
NguyenTrongLuat 
10
Daõy AND coù theå laäp 
trình 
Daõy OR coù theå laäp 
trình 
NguyenTrongLuat 
11
A Caáu truùc PLA 3 x 2, 4 soá 
F1 = A B + A C + A B 
CF2 = A C + B C 
0 
1 
haïng tích 
B 
C 
C C B B A A 
A B 
A C 
B C 
A B 
C 
F1 
F2 
Baûng naïp 
PLA A B C F2 (C) F1 
(T) 
1 0 
- 
A B 
A C 1 - 
B C 1- 1 
A B 1 
C 
0 1 
0 
0 
11 
11 
00 
NguyenTrongLuat 1 
12
PAL 
(PROGRAMMABLE ARRAY 
LOGIC ) 
- Daõy AND laäp trình, daõy OR coá ñònh 
- Moãi ngoõ ra laø coång OR coù soá ngoõ vaøo 
coá ñònh 
- Soá haïng tích khoâng söû duïng chung cho caùc 
ngoõ ra 
- Caáu truùc PLA: soá ngoõ vaøo, soá ngoõ ra vaø 
soá coång AND treân 1 coång OR 
NguyenTrongLuat 
13
Caáu truùc PAL 3 ngoõ vaøo, 3 ngoõ ra, 3 
coång AND / OR 
1 
2 
3 
4 
5 
6 
7 
8 
9 
I1 
I2 
I3 
F1 
F2 
F3 
NguyenTrongLuat 
14
A 
1 
2 
3 
4 
5 
6 
7 
8 
9 
B 
C 
X 
Y 
Z 
A A B B C C X X 
X = A B + 
B C 
Z = A B + B C + B C + 
A C 
Y = A + B C 
= X + B C + A C 
NguyenTrongLuat 
15
X = A B + 
B C 
Z = A B + B C + B C + 
A C 
Y = A + B C 
= X + B C + A C 
Baûng naïp 
PAL 
A B C 
X 
OUTPUT 
X = A B 
+ B 
C 
1 1 
1 1 
0 Y = A 
0 0 
+ B C 
Z = X 
1 0 0 
+ B C 
0 1 
+ A C 
1 
2 
3 
4 
56 
7 
8 
9 
NguyenTrongLuat 
16

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Kts c5-pld

  • 1. PLD THIẾT BỊ LOGIC LẬP TRÌNH ĐƯỢC (Programmable Logic Device) NguyenTrongLuat 1
  • 2. BOÄ NHÔÙ BAÙN DAÃN Boä nhôù baùn daãn Boä nhôù baûng Boä nhôù haøm RAM ROM tónh ñoäng MROM PROM EPROM EEPRO M PLD PLAPALLCA PPA LEPLPA LEEPPAL EPL D PEELGAL NguyenTrongLuat 2
  • 3. BOÄ NHÔÙ ROM Input: caùc tín hieäu ñòa chæ (Address) Output: caùc tín hieäu döõ lieäu (Data) A0 A1 An-1 D0 D1 Dm-1 INPUT (n ñöôøng) OUTPUT (m ñöôøng) Kích thöôùc ROM: 2n x m (bit) NguyenTrongLuat 3
  • 4. word line bit line 101 1 0 1 1 1 1 1 0 1 1 1 Baûng naïp ROM A2 A1 0 1 0 0 A0 D3 D2 D1 0 0 D0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 Caáu truùc noäi ROM 8 x 4 (bit) 1 NguyenTrongLuat 4
  • 5. ROM 128 x 1 (bit) giaûi maõ 2 chieàu NguyenTrongLuat 5
  • 6. ROM 32K x 8 (bit) = 32KB NguyenTrongLuat 6
  • 7. Caáu truùc ROM coù ngoõ vaøo ñieàu khieån NguyenTrongLuat 7
  • 8. Coång ñeäm ba traïng thaùi (Tristate Output Buffer): 3 traïng thaùi (tristate): LOW / HIGH / HIGH impedance Traïng thaùi toång trôû cao (HIGH impedance): ngoõ ra hôû maïch - Ngoõ ñieàu khieån 3 traïng thaùi: * HIGH: The buffer is Active * LOW: HIGH impedance NguyenTrongLuat 8
  • 9. Caùc EPROM thoâng duïng NguyenTrongLuat 9
  • 10. PLA (PROGRAMMABLE LOGIC ARRAY) INPUT (n bit) OUTPUT (m bit) k product term (soá haïng tích) Daõy AND Daõy OR NguyenTrongLuat 10
  • 11. Daõy AND coù theå laäp trình Daõy OR coù theå laäp trình NguyenTrongLuat 11
  • 12. A Caáu truùc PLA 3 x 2, 4 soá F1 = A B + A C + A B CF2 = A C + B C 0 1 haïng tích B C C C B B A A A B A C B C A B C F1 F2 Baûng naïp PLA A B C F2 (C) F1 (T) 1 0 - A B A C 1 - B C 1- 1 A B 1 C 0 1 0 0 11 11 00 NguyenTrongLuat 1 12
  • 13. PAL (PROGRAMMABLE ARRAY LOGIC ) - Daõy AND laäp trình, daõy OR coá ñònh - Moãi ngoõ ra laø coång OR coù soá ngoõ vaøo coá ñònh - Soá haïng tích khoâng söû duïng chung cho caùc ngoõ ra - Caáu truùc PLA: soá ngoõ vaøo, soá ngoõ ra vaø soá coång AND treân 1 coång OR NguyenTrongLuat 13
  • 14. Caáu truùc PAL 3 ngoõ vaøo, 3 ngoõ ra, 3 coång AND / OR 1 2 3 4 5 6 7 8 9 I1 I2 I3 F1 F2 F3 NguyenTrongLuat 14
  • 15. A 1 2 3 4 5 6 7 8 9 B C X Y Z A A B B C C X X X = A B + B C Z = A B + B C + B C + A C Y = A + B C = X + B C + A C NguyenTrongLuat 15
  • 16. X = A B + B C Z = A B + B C + B C + A C Y = A + B C = X + B C + A C Baûng naïp PAL A B C X OUTPUT X = A B + B C 1 1 1 1 0 Y = A 0 0 + B C Z = X 1 0 0 + B C 0 1 + A C 1 2 3 4 56 7 8 9 NguyenTrongLuat 16