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Top 20 vlsi interview questions and 
answers 
If you need top 7 free ebooks below for your job interview, please visit: 
4...
Tell me about yourself? 
This is probably the most asked 
question in vlsi interview. It breaks the 
ice and gets you to t...
Tell me some of constraints you used and their 
purpose during your design? 
There are lot of constraints and will vary fo...
What Can You Do for Us That Other Candidates 
Can't? 
What makes you unique? This 
will take an assessment of 
your experi...
Can you explain what struck at zero means? 
These stuck-at problems will appear in 
ASIC. Some times, the nodes will 
perm...
How do you handle complaints? 
The customers’ complaint about 
goods or services needs to follow the 
specific policies an...
What are dcm's?why they are used? 
Digital clock manager (DCM) is 
a fully digital control system that 
uses feedback to m...
what is slice,clb,lut? 
I am taking example of xc3s500 to 
answer this question 
The Configurable Logic Blocks 
(CLBs) con...
What is purpose of a constraint file what is its 
extension? 
The UCF file is an ASCII file 
specifying constraints on the...
How many global buffers are there in your 
current fpga,what is their significance? 
There are 8 of them in xc3s5000 
An e...
What are different types of timing verifications? 
Dynamic timing: 
a. The design is simulated in full timing 
mode. 
b. N...
What is the purpose of DRC? 
DRC is used to check whether the 
particular schematic and 
corresponding layout(especially t...
What is LVs and why do we do that. What is the 
difference between LVS and DRC? 
The layout must be drawn 
according to ce...
What is DFT ? 
DFT means design for testability. 'Design 
for Test or Testability' - a methodology that 
ensures a design ...
What is the significance of contamination delay in 
sequential circuit timing? 
The contamination delay of the data path i...
When are DFT and Formal verification used? 
DFT: 
· manufacturing defects like stuck 
at "0" or "1". 
· test for set of ru...
What is Synthesis? 
Synthesis is the stage in the design flow 
which is concerned with translating 
your Verilog code into...
How to write FSM is verilog? 
There r mainly 4 ways 2 write fsm code 
1) using 1 process where all input 
decoder, present...
Casex,z difference,which is preferable,why? 
CASEZ : 
Special version of the case statement which 
uses a Z logic value to...
What is the difference between wire and reg? 
Net types: (wire,tri)Physical connection 
between structural elements. Value...
What does `timescale 1 ns/ 1 ps signify in a 
verilog code? 
'timescale directive is a compiler 
directive.It is used to m...
Useful job interview materials: 
If you need top free ebooks below for your job interview, please visit: 
4career.net 
• F...
Top 6 tips for job interview 
Interview questions and answers – free pdf download Page 23 of 30
Tip 1: Do your homework 
You'll likely be asked difficult questions 
during the interview. Preparing the list of 
likely q...
Tip 2: First impressions 
When meeting someone for the first time, we 
instantaneously make our minds about various aspect...
good-first-impression-at-a-job-interview 
Tip 3: The “Hidden” Job Market 
Many of us don’t recognize that hidden job 
mark...
Tip 4: Do-It-Yourself Interviewing Practice 
There are a number of ways to prepare 
for an interview at home without the 
...
Tip 5: Ask questions 
Do not leave the interview without 
ensuring that you know all that you 
want to know about the posi...
Tip 6: Follow up and send a thank-you note 
Following up after an interview can 
help you make a lasting impression and 
s...
Interview questions and answers – free pdf download Page 30 of 30
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Top 20 vlsi interview questions and answers pdf ebook free download

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You'll likely be asked difficult questions during the interview. Preparing the list of likely questions in advance will help you easily transition from question to question.

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Top 20 vlsi interview questions and answers pdf ebook free download

  1. 1. Top 20 vlsi interview questions and answers If you need top 7 free ebooks below for your job interview, please visit: 4career.net • Free ebook: 75 interview questions and answers • Top 12 secrets to win every job interviews • 13 types of interview quesitons and how to face them • Top 8 interview thank you letter samples • Top 7 cover letter samples • Top 8 resume samples • Top 15 ways to search new jobs Interview questions and answers – free pdf download Page 1 of 30
  2. 2. Tell me about yourself? This is probably the most asked question in vlsi interview. It breaks the ice and gets you to talk about something you should be fairly comfortable with. Have something prepared that doesn't sound rehearsed. It's not about you telling your life story and quite frankly, the interviewer just isn't interested. Unless asked to do so, stick to your education, career and current situation. Work through it chronologically from the furthest back to the present. Interview questions and answers – free pdf download Page 2 of 30
  3. 3. Tell me some of constraints you used and their purpose during your design? There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx constraints a) Translate on and Translate off: the Verilog code between Translate on and Translate off is ignored for synthesis. b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify what input pin or internal net is the real clock signal. This constraint allows you to define the clock net. c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be collapsed into a single XOR. For more constraints detailed description refer to constraint guide. Interview questions and answers – free pdf download Page 3 of 30
  4. 4. What Can You Do for Us That Other Candidates Can't? What makes you unique? This will take an assessment of your experiences, skills and traits. Summarize concisely: "I have a unique combination of strong technical skills, and the ability to build strong customer relationships. This allows me to use my knowledge and break down information to be more user-friendly." Interview questions and answers – free pdf download Page 4 of 30
  5. 5. Can you explain what struck at zero means? These stuck-at problems will appear in ASIC. Some times, the nodes will permanently tie to 1 or 0 because of some fault. To avoid that, we need to provide testability in RTL. If it is permanently 1 it is called stuck-at-1 If it is permanently 0 it is called stuck-at-0. Interview questions and answers – free pdf download Page 5 of 30
  6. 6. How do you handle complaints? The customers’ complaint about goods or services needs to follow the specific policies and formalities. In order to make customers understand the process, I take them into each part and interpret clearly these guidelines. I do not show any ideas on the result of the complaint. This is the strict book method and it is the unique truly exact response. No ideas are suitable in such situation. Your idea about the result of the complaint should not be shown, because normally it does not depend on your decision. You can notify the customer’s rights and company rules. Interview questions and answers – free pdf download Page 6 of 30
  7. 7. What are dcm's?why they are used? Digital clock manager (DCM) is a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature and voltage. That is clock output of DCM is stable over wide range of temperature and voltage , and also skew associated with DCM is minimal and all phases of input clock can be obtained . The output of DCM coming form global buffer can handle more load. Interview questions and answers – free pdf download Page 7 of 30
  8. 8. what is slice,clb,lut? I am taking example of xc3s500 to answer this question The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. CLB are configurable logic blocks and can be configured to combo,ram or rom depending on coding style CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and G-LUT. Interview questions and answers – free pdf download Page 8 of 30
  9. 9. What is purpose of a constraint file what is its extension? The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Xilinx Constraints Editor to create constraints within a UCF(extention) file. These constraints affect how the logical design is implemented in the target device. You can use the file to override constraints specified during design entry. Interview questions and answers – free pdf download Page 9 of 30
  10. 10. How many global buffers are there in your current fpga,what is their significance? There are 8 of them in xc3s5000 An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global clock network or an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input. Interview questions and answers – free pdf download Page 10 of 30
  11. 11. What are different types of timing verifications? Dynamic timing: a. The design is simulated in full timing mode. b. Not all possibilities tested as it is dependent on the input test vectors. c. Simulations in full timing mode are slow and require a lot of memory. d. Best method to check asynchronous interfaces or interfaces between different timing domains. Static timing: a. The delays over all paths are added up. b. All possibilities, including false paths, verified without the need for test vectors. c. Much faster than simulations, hours as opposed to days. d. Not good with asynchronous interfaces or interfaces between different timing domains. Interview questions and answers – free pdf download Page 11 of 30
  12. 12. What is the purpose of DRC? DRC is used to check whether the particular schematic and corresponding layout(especially the mask sets involved) cater to a pre-defined rule set depending on the technology used to design. They are parameters set aside by the concerned semiconductor manufacturer with respect to how the masks should be placed , connected , routed keeping in mind that variations in the fab process does not effect normal functionality. It usually denotes the minimum allowable configuration. Interview questions and answers – free pdf download Page 12 of 30
  13. 13. What is LVs and why do we do that. What is the difference between LVS and DRC? The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by checking if the layout is abide by those rules. After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout with the schematic to ensure that the layout is an identical match to the cell schematic. Interview questions and answers – free pdf download Page 13 of 30
  14. 14. What is DFT ? DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design works properly after manufacturing, which later facilitates the failure analysis and false product/piece detection Other than the functional logic,you need to add some DFT logic in your design.This will help you in testing the chip for manufacturing defects after it come from fab. Scan,MBIST,LBIST,IDDQ testing etc are all part of this. (this is a hot field and with lots of opportunities) Interview questions and answers – free pdf download Page 14 of 30
  15. 15. What is the significance of contamination delay in sequential circuit timing? The contamination delay of the data path in a sequential circuit is critical for the hold time at the flip flop where it is exiting, in this case R2. mathematically, th(R2) <= tcd(R1) + tcd(CL2) Contamination delay is also called tmin and Propagation delay is also called tmax in many data sheets. Interview questions and answers – free pdf download Page 15 of 30
  16. 16. When are DFT and Formal verification used? DFT: · manufacturing defects like stuck at "0" or "1". · test for set of rules followed during the initial design stage. Formal verification: · Verification of the operation of the design, i.e, to see if the design follows spec. · gate netlist == RTL ? · using mathematics and statistical analysis to check for equivalence. Interview questions and answers – free pdf download Page 16 of 30
  17. 17. What is Synthesis? Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor. Interview questions and answers – free pdf download Page 17 of 30
  18. 18. How to write FSM is verilog? There r mainly 4 ways 2 write fsm code 1) using 1 process where all input decoder, present state, and output decoder r combine in one process. 2) using 2 process where all comb ckt and sequential ckt separated in different process 3) using 2 process where input decoder and persent state r combine and output decoder seperated in other process 4) using 3 process where all three, input decoder, present state and output decoder r separated in 3 process. Interview questions and answers – free pdf download Page 18 of 30
  19. 19. Casex,z difference,which is preferable,why? CASEZ : Special version of the case statement which uses a Z logic value to represent don't-care bits. CASEX : Special version of the case statement which uses Z or X logic values to represent don't-care bits. CASEZ should be used for case statements with wildcard don’t cares, otherwise use of CASE is required; CASEX should never be used. This is because: Don’t cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will automatically match any x or z with anything in the case statement. Casez will only match z’s -- x’s require an absolute match. Interview questions and answers – free pdf download Page 19 of 30
  20. 20. What is the difference between wire and reg? Net types: (wire,tri)Physical connection between structural elements. Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a->b, if there is no connection in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg is x. Interview questions and answers – free pdf download Page 20 of 30
  21. 21. What does `timescale 1 ns/ 1 ps signify in a verilog code? 'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage : `timescale / reference_time_unit : Specifies the unit of measurement for times and delays. time_precision: specifies the precision to which the delays are rounded off. Interview questions and answers – free pdf download Page 21 of 30
  22. 22. Useful job interview materials: If you need top free ebooks below for your job interview, please visit: 4career.net • Free ebook: 75 interview questions and answers • Top 12 secrets to win every job interviews • Top 36 situational interview questions • 440 behavioral interview questions • 95 management interview questions and answers • 30 phone interview questions • Top 8 interview thank you letter samples • 290 competency based interview questions • 45 internship interview questions • Top 7 cover letter samples • Top 8 resume samples • Top 15 ways to search new jobs Interview questions and answers – free pdf download Page 22 of 30
  23. 23. Top 6 tips for job interview Interview questions and answers – free pdf download Page 23 of 30
  24. 24. Tip 1: Do your homework You'll likely be asked difficult questions during the interview. Preparing the list of likely questions in advance will help you easily transition from question to question. Spend time researching the company. Look at its site to understand its mission statement, product offerings, and management team. A few hours spent researching before your interview can impress the hiring manager greatly. Read the company's annual report (often posted on the site), review the employee's LinkedIn profiles, and search the company on Google News, to see if they've been mentioned in the media lately. The more you know about a company, the more you'll know how you'll fit in to it. Ref material: 4career.net/job-interview-checklist- 40-points Interview questions and answers – free pdf download Page 24 of 30
  25. 25. Tip 2: First impressions When meeting someone for the first time, we instantaneously make our minds about various aspects of their personality. Prepare and plan that first impression long before you walk in the door. Continue that excellent impression in the days following, and that job could be yours. Therefore: · Never arrive late. · Use positive body language and turn on your charm right from the start. · Switch off your mobile before you step into the room. · Look fabulous; dress sharp and make sure you look your best. · Start the interview with a handshake; give a nice firm press and then some up and down movement. · Determine to establish a rapport with the interviewer right from the start. · Always let the interviewer finish speaking before giving your response. · Express yourself fluently with clarity and precision. Useful material: 4career.net/top-10-elements-to-make-a- Interview questions and answers – free pdf download Page 25 of 30
  26. 26. good-first-impression-at-a-job-interview Tip 3: The “Hidden” Job Market Many of us don’t recognize that hidden job market is a huge one and accounts for 2/3 of total job demand from enterprises. This means that if you know how to exploit a hidden job market, you can increase your chance of getting the job up to 300%. In this section, the author shares his experience and useful tips to exploit hidden job market. Here are some sources to get penetrating into a hidden job market: Friends; Family; Ex-coworkers; Referral; HR communities; Field communities; Social networks such as Facebook, Twitter…; Last recruitment ads from recruiters; HR emails of potential recruiters… Interview questions and answers – free pdf download Page 26 of 30
  27. 27. Tip 4: Do-It-Yourself Interviewing Practice There are a number of ways to prepare for an interview at home without the help of a professional career counselor or coach or a fee-based service. You can practice interviews all by yourself or recruit friends and family to assist you. Useful material: 4career.net/free-ebook- 75-interview-questions-and-answers Interview questions and answers – free pdf download Page 27 of 30
  28. 28. Tip 5: Ask questions Do not leave the interview without ensuring that you know all that you want to know about the position. Once the interview is over, your chance to have important questions answered has ended. Asking questions also can show that you are interested in the job. Be specific with your questions. Ask about the company and the industry. Avoid asking personal questions of the interviewer and avoid asking questions pertaining to politics, religion and the like. Ref material: 4career.net/25-questions-to- ask-employers-during-your-job-interview Interview questions and answers – free pdf download Page 28 of 30
  29. 29. Tip 6: Follow up and send a thank-you note Following up after an interview can help you make a lasting impression and set you apart from the crowd. Philip Farina, CPP, a security career expert at Manta Security Management Recruiters, says: "Send both an email as well as a hard-copy thank-you note, expressing excitement, qualifications and further interest in the position. Invite the hiring manager to contact you for additional information. This is also an excellent time to send a strategic follow-up letter of interest." Ref material: 4career.net/top-8- interview-thank-you-letter-samples Interview questions and answers – free pdf download Page 29 of 30
  30. 30. Interview questions and answers – free pdf download Page 30 of 30

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