VLSI SYSTEM Design, profile picture

VLSI SYSTEM Design

Sort by
SPEF format
Clk-to-q delay, library setup and hold time
Need of Decoupling Capacitor
Switching activity
Static Noise margin
Powerplanning
Place decap
Floorplan (http://www.vlsisystemdesign.com/PD-Flow.php)
Define location of Preplaced cells(http://www.vlsisystemdesign.com/PD-Flow.php)
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-Flow.php)
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)