1. PROGRAMMING ASSEMBLY
Lang., PROGRAMMING
CONCEPTS etc…
B. VENKANNA
(12MT06PED008)

2. INSIDE THE 8051

3. Memory in the 8051
 On-chip ROM ：To save your program
Program is burn in ROM.
Program is fixed and changeless.
 On-chip RAM：To save some temporary data generated in execution time
Data can be changed.
Data is lost when the 8051 powers down.
 Registers：To store information temporarily
Some registers are used for internal operations of the 8051.
Some registers are located in RAM. Some have their special locations.

4. Registers
 Register are used to store information temporarily.
 The 8051 has 8-bit registers and 16-bit registers.
A lot of 8-bit registers
Two 16-bit registers

5. 8-Bit Registers of the 8051
A Accumulator：for
B
R0
R1
R2
R3
R4
R5
R6
R7
all arithmetic and
logic instruction
Register 0－7：
a set of general-purpose
registers
Register B：for
arithmetic/logic
operation, ex:
MUL, DIV

6. 8051 16-bit Registers
• DPTR（data pointer）：The 16-bit address for the
data located in program (ROM)
– DPL：low byte of DPTR
– DPH：high byte of DPTR
• PC（program counter）：The address of the next
instruction
DPH DPL
PC (program counter)
DPTR
PC

7. 8-bit Register
• The 8051 use 8-bit data type.
– Example：integer and character are 8 bits.
• Any data larger than 8-bits must be broken
into 8-bit chunks before it is processed.
D7 D6 D5 D4 D3 D2 D1 D0
most significant bit
(MSB)
last significant bit
(LSB)

10.  A Program consists of 0’s and 1’s is called as “Machine
Language”.
 Assembly Languages were developed that provide “mnemonics”
for the machine code instructions.
 Assembly Language is a low-level language.
 Assembly Language Programs must be translated into machine
code by a program called an “Assembler”.
 High-level Languages are translated into machine code by a
program called a “Compiler”.

11. Assembly Language Program
• Why ? ? ?
More user friendly
Less error prone
To get compact code
Lesser memory
To get shorter execution time
Lower cost of implementation

12. ‣ Assembly language instruction format (4 fields)
[label:] mnemonic [operands] [;comment]
• [ ] indicate a field is optional
• A mnemonic (abbreviation easy to remember)
- optionally followed by one or two operands
- commands the CPU, telling it what to do with those items
‣ A given Assembly language program is a series of statements, or lines which
are either
• Assembly language instructions
- Tell the CPU what to do, such as ADD, MOV
• Directives (or pseudo-instructions)
- Give directions to the assembler, such as ORG,END

13. EExxaammppllee
ORG 0H ;start(origin) at location 0
MOV R5, #25H ;load 25H into R5
MOV R7, #34H ;load 34H into R7
MOV A, #Directives 0 ; do load not
0 into A
ADD A, R5 generate ; any add machine
contents of R5 to A ;now A=A+R5
ADD A, R7 code ; and are add used
contents of R7 to A ;now A=A+R7
ADD A, #only 12H by the assembler
;add to A value 12H ;now A = A + 12H
HERE: SJMP HERE ;stay in this loop
END ;end of asm source file
Mnemonics produce
opcodes
Comments may be at the
end of a line or on a line by
themselves. The assembler
ignores comments.
The label field allows
the program to refer to a
Labels must be unique and should enhanlcien reea doafb ilcityo. d Neam besy m anya inmcluede upper and lower case
letters, numbers, period(.), at sign(@) underscore (_), question mark(?) and dollar sign($).
The first character must be alphabetic character. You must avoid reserved words.

14. Assembling and Running an 8051
Program
Editor
Program
myfile.asm
Assembler
Program
myfile.obj
Linker
Program
myfile.abs
OH Program
myfile.hex
‣ Editor only enters ASCII chars into
file
• Textedit, EDIT, etc.
‣ Assembler converts mnemonics into
machine instructions (obj) and a list
file
• List file contains mnemonics
along with machine code (in
HEX) for debug purposes
‣ Linker connects (links) your object
file with others
‣ OH is the “Object to HEX”
conversion into format ready to
burn into our 8051 device
myfile.lst other obj files

15. Program Counter and ROM Code
‣ The Program Counter (PC) always points to the next instruction to
execute
‣ PC is zeroed (cleared) at RESET and thus fetches the instruction
located at location 0000H first
List File Memory
1 0000 ORG 0H ;start at location 0
2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A
6 0007 2F ADD A,R7 ;add contents of R7 to A
7 0008 2412 ADD A,#12H ;add 12H to A
8 000A 80FE HERE: SJMP HERE ;stay in this loop
9 000C END
0000 7D
0001 25
0002 7F
0003 34
0004 74
0005 00
0006 2D
0007 2F
0008 24
0009 12
000A 80
000B FE
Memory
Addresses
Hex
Obj. Code
Memory
Addresses
Hex
Obj. Code

16. Data Types and Directives
DB (Define Byte) and EQU (Equate)
• 8051 microcontroller is a 8 bits Processor
 The size of each register is also 8 bits
 It is the job of the programmer to break down data larger than 8 bits (00 to
FFH, or 0 to 255 in decimal)
 The data types used by the 8051 can be positive or negative
DB (Define Byte)
The DB directive is the most widely used data directive in the assembler
 It is used to define the 8-bit data
 When DB is used to define data, the numbers can be in decimal, binary, hex or
ASCII formats

17. DB Examples
ORG 500H
Data1: DB 28 ;DECIMAL (1CH)
Data2: DB 00110101B ;BINARY (35H)
Data3: DB 39H ;HEX
ORG 510H
Nums: DB “2591” ;ASCII NUMBERS
ORG 518H
My_Name: DB “My name is Joe” ;ASCII CHARACTERS
Count EQU 25 ;REPLACE COUNT w/ 25
…
MOV R3,#COUNT ;MOVE 25D into R3
Memory
0500 1C 28d
0501 35 53d
0502 39 57d
: :
0510 32 ‘2’
0511 35 ‘5’
0512 39 ‘9’
0513 31 ‘1’
: :
0518 4D ‘M’
0519 79 ‘y’
051A 20 <sp>
051B 6E ‘n’
051C 61 ‘a’
051D 6D ‘m’
051E 65 ‘e’
051F 20 <sp>
0520 69 ‘i’
0521 73 ‘s’
0522 20 <sp>
0523 4A ‘J’
0524 6F ‘o’
0525 65 ‘e’
0526 19 25d
0527 :

18. Assembler directives
 ORG (origin)
 The ORG directive is used to indicate the beginning of the address
 The number that comes after ORG can be either in hex and decimal
 END
 This indicates to the assembler the end of the source (.asm) file
 END mean that in the source code anything after the END directive is ignored by the
assembler
 EQU (equate)
This is used to define a constant without occupying a memory location
Data: EQU 25
MOV R3, #Data

19. Addressing Modes
1. immediate － the operand is a constant
MOV A,#01FH
2. register － the operand is in a register
MOV A,R0
3. direct － access the data in the RAM with address
MOV A,01FH
4. register indirect － the register holds the RAM address of the data
MOV A,@R0
5. indexed － for on-chip ROM access
MOVC A,@A+DPTR

20. Register Addressing Mode
MOV Rn, A; ;n=0,..,7
ADD A, Rn;
MOV DPL, R6;
MOV DPTR, A

21. Instruction Format
1.One/single byte instruction.
2.Two/double byte instruction.
3.Three/triple byte instruction.

22. Instruction Format
1. One/single byte instructions :
• If operand is not given in the instruction or there is no
digits present with instruction, the instructions can be
completely represented in one byte opcode.
• OPCODE 8 bit
B7 B0
1-Byte ---------- 49
OOppccooddee
(Instructions)

23. Instruction Format
2. Two/double byte instruction:
 If 8 bit number is given as operand in the instruction, the such
instructions can be completed represented in two bytes.
 First byte OPCODE
 Second byte 8 bit data or I/O port
B7 B0
OOppccooddee
1-Byte ---------- 45
DDaatata (Instructions)

24. Instruction Format
3. Three/triple byte instruction:
• If 16 bit number is given as operand in the instructions than such
instructions can be completely represented in three bytes 16 bit number
specified may be data or address.
• First byte OPCODE.
• Second byte 8 LSB’s of data/address.
• Third byte 8 MSB’S of data/address
B7 B0
OOppccooddee
1-Byte ---------- 17
Data (Instructions)

25. Instruction Format
• Total number of instructions=111
• Execution time is directly proportional to the size
of the instruction.

26. Types of Instruction Sets
1. Data transfer instructions.
2. Arithmetic instructions.
3. Logical instructions.
4. Control Transfer instructions.

27. Direct Data
Register
C
Register
R7-R0 Direct Data
Register Indirect
@R1, @R0
Register
A
Register
DPTR
Immediate Data
Register Indirect
@SP
Types of Instruction Sets
1. Data Transfer Instructions
i. MOV

28. Register
R7-R0 Direct Data
Register
A
8 4
Register Indirect
@R1, R0
XCH A, R0
XCH A, 40H
XCH A, @R1
XCHD A, @R0
Exchange

29. The 8051 Instructions
8051 Instruction Set Summary
1. Data Transfer：get or store data
– MOV, PUSH, POP
2. Arithmetic Operations：
– ADD, SUB, INC, DEC, MUL, DIV
3. Logical Operations：
– ANL, ORL, XRL, CLR
4. Program Branching：jump, loop, call instruction
– LCALL, RET, LJMP, JZ, JNZ, NOP

30. 8051 Instruction Set
ACALL: Absolute Call
ADD, ADDC: Add Acc. (With Carry)
AJMP: Absolute Jump
ANL: Bitwise AND
CJNE: Compare & Jump if Not Equal
CLR: Clear Register
CPL: Complement Register
DA: Decimal Adjust
DEC: Decrement Register
DIV: Divide Accumulator by B
DJNZ: Dec. Reg. & Jump if Not Zero
INC: Increment Register
JB: Jump if Bit Set
JBC: Jump if Bit Set and Clear Bit
JC: Jump if Carry Set
JMP: Jump to Address
JNB: Jump if Bit Not Set
JNC: Jump if Carry Not Set
JNZ: Jump if Acc. Not Zero
JZ: Jump if Accumulator Zero
LCALL: Long Call
LJMP: Long Jump
MOV: Move Memory
MOVC: Move Code Memory
MOVX: Move Extended Memory
MUL: Multiply Accumulator by B
NOP: No Operation
ORL: Bitwise OR
POP: Pop Value From Stack
PUSH: Push Value Onto Stack
RET: Return From Subroutine
RETI: Return From Interrupt
RL: Rotate Accumulator Left
RLC: Rotate Acc. Left Through Carry
RR: Rotate Accumulator Right
RRC: Rotate Acc. Right Through Carry
SETB: Set Bit
SJMP: Short Jump
SUBB: Sub. From Acc. With Borrow
SWAP: Swap Accumulator Nibbles
XCH: Exchange Bytes
XCHD: Exchange Digits
XRL: Bitwise Exclusive OR
Undefined: Undefined Instruction

31. RAM Allocation in the 8051
RAM in the 8051
• 128 bytes of RAM in the 8051
• These 128 bytes are divide into three different groups:
– 32 bytes for register banks and the stack
• 00 to 1FH RAM
– 16 bytes for bit-addressable read/write memory
• 20H to 2FH RAM
– 80 bytes for scratch pad
• 30H to 7FH RAM

32. RAM Allocation in the 8051
7F
30
2F
20
1F
18
17
10
0F
08
07
00
Scratch pad RAM
Bit-Addressable RAM
Register Bank 3
Register Bank 2
Register Bank 1
(stack)
Register Bank 0
Register
Banks
and the
stack

33. R0 to R7
• The 8051 uses 8 registers as general register.
– They are named as R0,R1,...,R7.
– They form a register bank.
• The 8051 provides 4 banks
Bank 0 Bank 1 Bank 2 Bank 3
00-07H 08H-0FH 10H-17H 18H-1FH
• Where is the address of R0?

34. 8051 Register Banks and their RAM
Addresses
Bank 0 Bank 1 Bank 2 Bank 3
07 R7 0F R7 17 R7 1F R7
06 R6 0E R6 16 R6 1E R6
05 R5 0D R5 15 R5 1D R5
04 R4 0C R4 14 R4 1C R4
03 R3 0B R3 13 R3 1B R3
02 R2 0A R2 12 R2 1A R2
01 R1 09 R1 11 R1 19 R1
0 R0 08 R0 10 R0 18 R0

35. Register Banks
• RS1 and RS0 decide the bank used by R0-R7.
– RS1 and RS0 are bits 4 and 3 of PSW register, respectively.
• Default register bank ：
– When the 8051 is powered up, RS1=RS0=0. That is, the RAM locations 00-07H
are accessed with R0-R7.
– If we don’t change the values of RS1 and RS0, we use the default register bank:
Bank 0.
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

36. Stack in the 8051
• The register used to access
the stack is called SP
(stack pointer) register.
• The stack pointer in the
8051 is only 8 bits wide,
which means that it can
take value 00 to FFH.
When 8051 powered up,
the SP register contains
value 07
7FH
30H
2FH
20H
1FH
18H
17H
10H
0FH
08H
07H
00H
Scratch pad RAM
Bit-Addressable RAM
Register Bank 3
Register Bank 2
Stack) Register )
Bank 1
Register Bank 0

37. Example:
MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4
0BH
0AH
09H
08H
Start SP=07H
25
0BH
0AH
09H
08H
SP=08H
F3
12
25
0BH
0AH
09H
08H
SP=08H
12
25
0BH
0AH
09H
08H
SP=09H

38. 38

39. 39
Bit-addressable RAM
• The bit-addressable RAM locations are 20H to
2FH.
• Only 16 bytes of RAM are bit-addressable.
– 16 * 8 bits = 128 bits (in decimal) = 80H bits (in hex)
– They are addressed as 00 to 7FH
– Note that the bit addresses 80H to F7H belong to SFR.

40. 40
Bytes of Internal RAM
General purpose RAM
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
17 16 15 14 13 12 11 10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
Bank 3
Bank 2
Bank 1
Default register bank for R0 - R7
7F
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
1F
18
17
10
0F
08
07
00
Byte address
acol el basser dda-ti B

42. Flag Bits and Program Status Word (PSW)
• The Program Status Word (PSW) register, also referred
to as the flag register, is an 8 bit register
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV -- P
• CY PSW.7 Carry Flag
• AC PSW.6 Auxiliary Carry Flag
• F0 PSW.5 Available to user for general purpose
• RS1 PSW.4 Register Bank Selector bit 1
• RS0 PSW.3 Register Bank Selector bit 0
• OV PSW.2 Overflow flag – Signed arithmetic error indicator
• -- PSW.1 User definable bit
• P PSW.0 Parity Flag – 0: ACC has even # of 1’s, 1: ACC has odd # of 1’s
Each 8051 instruction will indicate whether or not and which Flag Bits are set

43. PSW and Flag Bits
– Only 6 bits are used by 8051
• Among four are CY (carry), AC (auxiliary carry), P
(parity), and OV (overflow)
• They are called conditional flags, meaning that they
indicate some conditions that resulted after an
instruction was executed
– The PSW.3 and PSW.4 are designed as RS0 and RS1, and are used to
change the bank registers
– The PSW.5 and PSW.1 are user-definable

45. Instructions That Affect Flag Bit

46. How to Switch Register Banks
• Usually, 8 data is not enough.
• Bits D4 and D3 of the PSW are used to select the desired register
bank.
– D4 is referred to as PSW.4 （RS1）
– D3 is referred to as PSW.3 （RS0）
• Use SETB and CLR
SETB PSW.4 ;set RS1=1
CLR PSW.3 ;clear RS0=0
– Choose Bank 2（Addresses: 10F-17H for R0-R7）

47. Example
State the contents of RAM locations after the following program:
MOV R0,#99H ;load R0 with value 99H
MOV R1,#85H ;load R1 with value 85H
MOV R2,#3FH ;load R2 with value 3FH
MOV R7,#63H ;load R7 with value 63H
MOV R5,#12H ;load R5 with value 12H
Solution:
After the execution of above program we have the following:
RAM location 0 has value 99H RAM location 1 has value 85H
RAM location 2 has value 3FH RAM location 7 has value 63H
RAM location 5 has value 12H

48. Example
Repeat Example using RAM addresses instead of register names.
Solution:
This is called direct addressing mode and uses the RAM address
location for the destination address. See Chapter5 for a more detailed
discussion of addressing modes.
MOV 00,#99H ;load R0 with value 99H
MOV 01,#85H ;load R1 with value 85H
MOV 02,#3FH ;load R2 with value 3FH
MOV 07,#63H ;load R7 with value 63H
MOV 05,#12H ;load R5 with value 12H

49. Example
State the contents of the RAM locations after the following
program:
SETB PSW.4 ;select bank 2
MOV R0,#99H ;load R0 with value 99H
MOV R1,#85H ;load R1 with value 85H
MOV R2,#3FH ;load R2 with value 3FH
MOV R7,#63H ;load R7 with value 63H
MOV R5,#12H ;load R5 with value 12H
Solution:
By default, PSW.3=0 ＆ PSW.4=0
“SETB PSW.4” sets RS1=1 and RS0=0 Þ Register bank 2.
Register bank 2 uses RAM locations 10H – 17H.
RAM location 10H has value 99H RAM location 11H has value 85H
RAM location 12H has value 3FH RAM location 17H has value 63H
RAM location 15H has value 12H