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RCW@DEI - Design Flow 4 SoPc

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Marco Santambrogio
Marco Santambrogio
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Design Flow for SoPC P artial D ynamic R econfiguration W orkshop DRESD Team [email_address]
Motivations ,[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object]
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Xilinx FPGA technology
CLB Switch Box SLICE TBUF Y X 67 66 75 74 SLICE_X66Y74
The configuration bitstream ,[object Object],[object Object],[object Object]
Frame and Configuration Memory ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Xilinx FPGA and configuration memory
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Difference based (Smallbit) ,[object Object],[object Object],[object Object]
Pre – Partial Reconfiguration ,[object Object]
Post – Partial Reconfiguration ,[object Object]
Module based 1/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Module based 2/3 ,[object Object],[object Object],[object Object]
Module based 3/3 ,[object Object],1 2 HDL description and synthesis Initial Budgeting Phase (define design constraint) 3 Active Module Phase (implementation of each component) 4 Final Assembly Phase (asseble individual modules togheter)
Pre – Partial Reconfiguration Xilinx S3 FPGA
Post – Partial Reconfiguration Xilinx S3 FPGA
EAPR 1/3 ,[object Object],[object Object],[object Object],[object Object],[object Object]
EAPR 2/3 ,[object Object],1 2 HDL description and synthesis Define design constraint (text editor, Floorplanner...) 3 Implement base design (static) 4 Implement PRM design 5 Merge phase: PRM + base
EAPR 3/3 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Pre – Partial Reconfiguration ,[object Object]
Post – Partial Reconfiguration Xilinx Virtex 4 FPGA
What’s next ,[object Object],[object Object],[object Object],[object Object]
Design Flow: Challenges and Rationale ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
What’s next ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
INCA ,[object Object],[object Object],[object Object],[object Object],[object Object]
Low-Level design flow: Caronte ,[object Object],[object Object],[object Object]
Hardware Side – design flow
Low-Level Design: Contributions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
System Description
Area Constraints Xilinx VIIP Xilinx S3 Xilinx V4
Reconfigurable Region Definition ,[object Object],AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP "RR1" RANGE = RAMB16_X2Y9:RAMB16_X2Y15;
Design Synthesis and Placement Constraints Assignment
System Generation Context Creation: EAPR-based
[object Object],[object Object],[object Object],[object Object],YaRA v1: 1D, Whishbone BUS-based YaRA v2: 2D,CoreConnect-based The DRESD reconfigurable architecture
Software Side – Standalone Solution
Software side of the Caronte flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfiguration Support ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IP-Core devices access ,[object Object],[object Object]
Reconfigurable Process Control Block ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Centralized Manager ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Software Side – Linux Solution
Concluding Remarks: Top Ten Reasons to work in Caronte and OSyRiS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Treasure Hunt ,[object Object],[object Object],[object Object],[object Object],[object Object]
Questions

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RCW@DEI - Design Flow 4 SoPc