3DD1e JHDL

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Marco Santambrogio

Tecnologia Design

JHDL - Just another Hardware Description Language - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio

The Problem Efficiency in Core development VHDL: - needs to be learned - is difficult to learn - is difficult to debug

The Solution Improve Acheronte Core Development Exploit JHDL : a Java-based tool-suite / design-environment

JHDL Pros ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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JHDL in Acheronte: Simple

JHDL in Acheronte: more advanced

Conclusion ,[object Object],[object Object],[object Object],[object Object],[object Object]

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For a long ago, world of digital design has spread out in the many major and a lot of logics, approaches, and theories has been proposed. The digital emerges as a solution of a daily-life need and applicable on such technology from the developing devices until software-based. All of the designs has a significant point on the spesification, integration, and optimization. The designers have been trying to make a good designs on both hardware and software, latest both combinations have been known as the basic idea of hardware/ software co-design. The state-of-the art computer is very interesting to research because of its implementation can make changes of the cycle of reconfigurable objects. This paper presents a comparison of the two role plays in reconfigurable devices especially FPGA-based, i.e. Altera and Xilinx. The idea is that of a simple compiler has a good performance designs for synthesizing Very high speed integrated circuit Hardware Description Language (VHDL) code as well as the other complexity software that more powerful. So, this paper proposes such method as interoperability for reconfiguring devices to get the point why few of the standard VHDL code can’t be synthesised in the different compiler of VHDL code between Xilinx and Altera. The project of compiler softwares that is observed from Xilinx is ISE and from Altera is Max+Plus II. Max+Plus II is a low-cost software than ISE Xilinx, although both Xilinx and Altera devices have a different structure each other.

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3DD1e JHDL

1. JHDL - Just another Hardware Description Language - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio

2. The Problem Efficiency in Core development VHDL: - needs to be learned - is difficult to learn - is difficult to debug

3. The Solution Improve Acheronte Core Development Exploit JHDL : a Java-based tool-suite / design-environment

4.

6. JHDL in Acheronte: Simple

7. JHDL in Acheronte: more advanced

8.