Elixirでハードウェアが作れちゃう，かも！！？データフロー型ハードウェア設計環境Cockatriceのご紹介

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always@(posedge clk) begin
if (!rst) out <= 0;
else begin
case (in)
4'b0001 : tmp <= 1;
4'b0010 : tmp <= 5;
4'b1100 : tmp <= 7;
default : tmp <= 0;
endcase
end
end
assign out = ~{reg[7:4], tmp[3:0]};
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Elixirでハードウェアが作れちゃう，かも！！？データフロー型ハードウェア設計環境Cockatriceのご紹介

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