Differential amplifiers

1. Differential Amplifiers:
Second Stage
Dr. Paul Hasler

2. Differential Transistor Pairs
MOSFET Diff-Pair BJT Diff-Pair
The bottom transistor (the one with Ibias) sets the total current
The upper two transistors compete for a fraction of this current

3. BJT Differential Pair Analysis

4. Analysis of Diff-Pair
Source of Common-Mode Gain

5. Differential Pair Currents
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
0
0.5
1
1.5
2
2.5
3
Differential input voltage (V)
Output
current
(nA)
Iout
+
Iout
-

6. Above VT MOSFET Large-Signal

7. Above VT MOSFET Large-Signal
vID  vGS1  vGS2 






2iD1

1/2







2iD2

1/2
ISS  iD1 + iD2
Start with 2 equations

8. Above VT MOSFET Large-Signal
vID  vGS1  vGS2 






2iD1

1/2







2iD2

1/2
ISS  iD1 + iD2
Start with 2 equations

9. Above VT MOSFET Large-Signal
iD1 
ISS
2 +
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
iD2 
ISS
2 
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
vID  vGS1  vGS2 






2iD1

1/2







2iD2

1/2
ISS  iD1 + iD2
Start with 2 equations

10. Above VT MOSFET Large-Signal
iD1 
ISS
2 +
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
iD2 
ISS
2 
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
vID  vGS1  vGS2 






2iD1

1/2







2iD2

1/2
ISS  iD1 + iD2
Start with 2 equations
gm  iD1/vID(VID  0)  (ISS/4)1/2 






K'1ISSW1
4L1
1/2

11. Above VT MOSFET Large-Signal
iD1 
ISS
2 +
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
iD2 
ISS
2 
ISS
2






v
2
I D
ISS

2v
4
I D
4I
2
SS
1/2
vID  vGS1  vGS2 






2iD1

1/2







2iD2

1/2
ISS  iD1 + iD2
Start with 2 equations
gm  iD1/vID(VID  0)  (ISS/4)1/2 






K'1ISSW1
4L1
1/2

13. Gain Changes with Bias Current

14. Common-Mode Input Range
Maximum: Q1 in Forward-active Minimum: Q3 in Forward-active

15. MOS Common-Mode Input Range
Maximum: M1 in Saturation Minimum: M3 in Saturation
vic(max) = VDD - 0.5ISSRD -vDS1(sat)+VGS1
= VDD - 0.5ISSRD + VT1
vic(min) = VSS+vDS3(sat)+VGS1

16. Micro-Surgery

17. Small Signal: BJT Diff-Pair

18. Common-Mode Circuit

19. Common-Mode Circuit
An emitter-degenerated amplifier
Gain ~ - Rc / (2 REE)

20. MOS Common-Mode Circuit

21. MOS Common-Mode Circuit
An emitter-degenerated amplifier
Gain ~ - RD / (2 Rss)

22. Differential-Mode Gain

23. Differential-Mode Gain
Gain = - gm Rc CMRR ~ - 2 gm RE
~ - 2 (IEE/ 2 UT) RE

24. MOS Differential Mode Circuit

25. MOS Differential Mode Circuit
Gain = - gm RD CMRR ~ - gm Rss
~ - (Iss/ ( Vgs - VT) ) Rss

26. Mismatch in Transistor Circuits
Outline
The general approach to analyzing mismatches
Input voltage and current offsets of BJT differential amplifiers
Input voltage offsets of MOS differential amplifiers
Objective
The objective of this presentation is:
1.) Illustrate the method of analyzing mismatches
2.) Analyze the input current and voltage offsets for differential amplifiers

27. BJT Mismatch Modeling

28. Mismatch Modeling in MOS

29. BJT Mismatch Modeling

30. Differential Amplifiers II
• Review of Basic Differential Pairs
• Above Threshold Differential Amplifiers
• Small-Signal Analysis: Differential and
Common mode circuits
• Modeling of Mismatch