lecture4.ppt

RFIC Design
Lecture 4:
Transceiver Architecture

RFIC Design
4: Transceiver Architecture Slide 2
Outline
 Receiver :
– Linearity -> IP3, P1dB
– Noise -> SNR
– Sensitivity & Dynamic Range
– Channel filtering
 Transmitter

RFIC Design
Nonlinearity
 For nonlinear amplifier, its TF can be represented
as :
 If
 Results in Harmonics.
 Higher order harmonics contain higher power of A

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Odd symmetry
 Differential or Balanced Circuit
 Even order terms disappear
 Even harmonics are absent

RFIC Design
1-dB compression point
 The input level that causes the small-signal gain to
drop by 1dB.
 Because of : Nonlinearity
 Around -25~-20dBm(63.2m ~ 35.6mV in 50Ω system)

RFIC Design
Desensitization and Blocking
 Cause : A small signal is received and accompanied
with a strong interference.
 If a3 is negative, then gain is reduced.
 RF receiver must withstand 60~70dB signal
difference.

RFIC Design
Cross Modulation
 Nonlinear effect
 Cause : A small signal is received and accompanied
with a strong interference.
 If and

RFIC Design
Intermodulation(I)
 Harmonics distortion is not very useful to
characterize nonliearity.
 ∵ For examples, a low pass filter reduce the
hamonics.

RFIC Design
Intermodulation(II)
 Perform “two-tone” test.
 If
 Then main part
 and harmonics

RFIC Design
Intermodulation(III)
 We call the components at and the 2w1±w2 and
2w2±w1 third-order intermodulation products
 Note the 2w1- w2 and 2w2- w1 tone. It comes
closest to the main tone due to nonlinearity effect.
 Ex : A1=A2, if a1A=1V and a3A3/4=10mV
then we say IM componet is -40dBc, where c means
with respect to the carrier.

RFIC Design
Intermodulation(IV)
 IM is a troublesome effect in RF system.
 IM causes a weak signal is corrupted by two strong
interference.
 While operating by AM, it still degrades the PM.
Because zero-crossing points are still affected.
 The effect can not be observed from Harmonic
distortions.

RFIC Design
Intermodulation(V)
 IP3 : Third intercept point
 It is very useful to characterize the linearity
IM3 component increases with A3.
 IIP3 is the input IP3 and OIP3 is at output.
 Figures (a) in linear scale and (b) in log scale.

RFIC Design
Intermodulation(VI)
 How to calculate IP3
 Let
 Suppose
 then

RFIC Design
Intermodulation(VII)
 How to measure IIP3 with a single measurement
 While
 then

RFIC Design
Intermodulation(VIII)
 How to calculate SNR for IM effect
 Suppose
 Then
 Ex.

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IIP3 & P1dB
 The theoretically relationship is

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Cascade Nonlinear Stages
 If
 then

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Cascade Nonlinear Stages
 Practical usage :
 Approximation:
 More cascade stages

RFIC Design
General Considerations
 Receiver :
– Noise -> NF

RFIC Design
Thermal Noise
 The PDF is Gaussian
 The PSD is given by:
– Mean square noise voltage

RFIC Design
Thermal Noise
 In the MOSFET
 Short channel: g > 2 ( process dependent )
 Long channel: g =2/3

RFIC Design
Flicker noise
 Flicker noise
 It arise from random trapping of charge at the
oxide-silicon interface of MOSFETs.
 K is a constant and process dependant.

RFIC Design
Shot noise
 If carriers cross a potential barrier, then the overall
current actually consists of a large number of
random current pulses.
 Usually exists in the BJT
 The random component of the current is called “shot
noise” .
 It is

RFIC Design
Input Referred Noise
 The overall noise of a circuit can be represented by only two
sources placed at the input:
 Ex.
 Note: The two sources are correlated here because they
represent the same mechanism.

RFIC Design
Noise Figure
 NF is a measure of how much the SNR degrades as
the signal passes through system.
 Definition :
 Usually in dB unit ( 10log10)
 NF > 1
 If no input noise, NF -> ∞. (not meaningful)

RFIC Design
Noise Figure Calculation
(for measurement)

RFIC Design
Noise Figure Calculation
 Ex. : In 50ohm system
What is the NF?

RFIC Design
Noise Figure of Cascaded Stages
 NF calculation

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 For a special case :

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 For general case :
 (1)
 (2)
 (1)+(2)
 Friis equation:
Available
power gain
Available power

RFIC Design
Noise Figure of Lossy circuit
 Consider a lossy circuit
 Finally, we get NF = L
 Ex. If a BP filter has 3dB loss, its NF is 3dB

RFIC Design
Noise Figure of Lossy circuit
 Consider a lossy circuit in the receiver chain :
 We get
 Ex : If the BP filter has 1dB loss followed by LNA with 3dB NF,
then the total NF is 4dB.
 Hence : the first filter plays a very important role for the receiver
noise performance.

RFIC Design
 Receiver :
– Noise -> NF

RFIC Design
Sensitivity
 From NF :
 We get :
 Because the RF is 50ohm system :
 Then :
,where B is bandwidth

RFIC Design
Sensitivity Calculation
 Ex.:For GSM,SNRmin ~ 12dB, B = 200kHz
 If NF of the receiver path is 9dB,
Then : Sensitivity is -174+9+53+12 = -100 dBm
 If we have a specification with sensitivity of -105dBm,
Then : NF should be : -105+174-53-12 = 4dB

RFIC Design
SFDR
 The upper end of DR (actually “spurious-free”
dynamic range,(SFDR) is defined as the max.
 IM <= the noise floor:
 where Noise floor=-174 dBm+NF+10log B
 Then :

RFIC Design
SFDR
 Example: GSM,SNRmin ~ 12dB, B = 200kHz, NF is
9, suppose IIP3 =-15 dBm.
 Then, SFDR=2/3(-15-(-112))-12=52.7 dB
 SFDR indicates how much interference the system
can tolerate while providing an acceptable signal
quality.

RFIC Design
 Desensitization of LNA from PA
– PA output 1W (30dBm)
– 25dBm ANT by duplexer
– LNA is with P1db of -26dBm

RFIC Design
 Receiver :
– SNR
– Linearity -> IP3
– Channel filtering -> Receiver Architecture

RFIC Design
Channel filtering
 Receiver :
– Interference Rejection
• High Q filter
• Ex : 900MHz receiver with 60db ANT of 90kHz
=> Q:~1E7

RFIC Design
Channel filtering
 Receiver :
– Bandpass filter selection
• Tradeoff : In-band Loss & Out-band Rejection
• In-band Loss => High Noise (NF) & Low SNR

RFIC Design
Channel filtering
 Receiver :
– Band Selection
– Channel Selection
 Reject image
 Relax linearity requirement

RFIC Design
Heterodyne Receiver
 Heterodyne : the signal band is translated to much
lower frequencies (IF) so as to relax the Q required
of the channel-select filter.
 IF : intermediate frequency.
 It filters out some strong interference to relax the
linearity requirement for the following stages.

RFIC Design
Problem of image
 Both desirable and undesirable frequency band are
all mixed down to IF
 Solution : We need proper “image rejection”

RFIC Design
Image rejection
 Trade-off for IF frequency selection
 High IF: good image rejection, poor channel selection
 Low IF : good channel selection, image rejection

RFIC Design
Image rejection
 High side injection : if wLO > win, then image is higher
than wLO.
 Low side injection : if wLO < win, then image is lower
than wLO.
 High side injection needs high VCO frequency
operation.
 Another consideration depends on the distribution of
image band noise.

RFIC Design
Half IF
 If an interference is at , the signal is
down-converted to half IF .
 If the following stage suffers from nonlinearity effect,
the second order distortion of the half IF will fall
down the wanted IF band.

RFIC Design
Heterodyne Receiver
 To enhance the sensitivity and selectivity,
heterodyne receiver downconverts signal two times.

RFIC Design
Homedyne Receiver
 It converts the RF signal once to the baseband.
 Called Homedyne , direct-conversion, zero-IF
architecture.
 In Fig.(a), it operates properly on with double –side band
AM signal because it overlaps + and - input spectrum.
 FM & QPSK has the different spectrum in the upper and
lower band. Hence , quadrature modulation is necessary.
 Fig.(b) operated for the quadrature modulation.

RFIC Design
Homedyne Receiver
 Advantages:
– No image
– Need no image rejection filter
– Monolithic integration
– LNA need no 50ohm output matching
 Disadvantage :
– DC offset
– IQ mismatch
– Filter noise
– LO leakage

RFIC Design
DC offset
 DC offset is very important issue for zero-IF.
– It corrupts the signal.
– It saturates the following stages.
 It arise from :
– Device mismatch
– self-mixing
– Signal reflection
– Tx leaks to RX

RFIC Design
DC offset
 (a) Self-mixing of LO signal
 (b) Strong interferer from input

RFIC Design
LO Leakage
 LO Leakage : It may arise from the mismatch of the
mixer or VCO without 50% duty cycle.

RFIC Design
DC offset
 Ex. DC offset arises from LO leakage :
– The VCO has 0dBm ( ~0.63V)
– After 60dB attenuation, it remain -60dBm before
LNA
– After amplified 30dB by LNA/MIXER , it becomes
10mV.
– At the meantime , the received signal is usually
30uVrms.
– Hence, the received signal need 50~70dB gain.
– Then such gain will let dc offset saturate the
amplifier chain.

RFIC Design
DC offset Cancellation
 Solution 1: High pass filter can cancel DC offset
– Issue 1: Around dc signal also loses engery.
– Issue 2: A larger capacitor fail to track fast
variation in the offset voltage.
 Solutions 2 : DC free coding
– A modulation or coding method carries little
signal around the DC
– Suitable for wideband signal
 Solution 3 : Stores the dc offset
– In the TDMA system, the dc offset value can be
stored in the C1 with a switch S1.

RFIC Design
DC offset Cancellation
 Issue 3:
– Mandating large C1 due to thermal noise kT/C.
– Offset due to VCO can be detected and stored.
– However, interferer signal randomly appears.
– Hence, averaged dc offset value is necessary.
stored cancelled

RFIC Design
I/Q mismatch
 A homodyne incorporates Quadrate mixing for the
frequency and phase modulation scheme.
 Scheme (b) is preferred due to not interfering the
main signal path.

RFIC Design
I/Q mismatch

RFIC Design
Even Order Distortion
 Even Order Distortion : If two strong interferers pass
through a nonlinear , then even order harmonics
appear in the low frequency and distort the down-
converted IF signal.

RFIC Design
Even Order Distortion
 IP2 : It is used to characterize even order distortion
 Solutions : Differential circuits
– Issue 1 : The front end antenna and duplexer are
usually single ended.
• Hence : Transformer is necessary for single to
differential but its loss causes higher NF.
– Issue 2 : Differential circuits consume more
power.

RFIC Design
Flicker Noise
 Flicker noise :
– Its noise power is proportional to 1/f.
– It corrupts input signal significantly around DC
frequency.
– In the homedyne receiver the down-converted
signal is only amplified LNA & Mixer (~30dB).
Hence signal is still very small and prone to
corrupted by the flicker noise.
 Solution : incorporate large device size to minimize
the magnitude of flicker noise.

RFIC Design
Architecture of Image
Reject Receiver

RFIC Design
90° shift circuit
 A narrow band shifted by 90 ° if its spectrum is
multiplied by G(w)=-j*sgn(w), where sgn(w) is called
signum function.
 90° shift : sinwt => -coswt
Vout1 :π /2 – tan-1RCω
Vout2 : – tan-1RCω

RFIC Design
Hartley Architecture

RFIC Design
 Graphical
Analysis
 Issues:
- Gain mismatch
- Phase mismatch

RFIC Design
 To analyze the effect of the phase and gain mismatch


RFIC Design

RFIC Design
 For
 For general case : Resistor variation in the CMOS
process is usually 20%
 Hence : It limits the IRR to only 20dB

RFIC Design
Weaver Architecture
 Weaver Architecture performs similar the technique
of 90° shift to cancel the image signal.

RFIC Design
Weaver Architecture
 Graphical analysis

RFIC Design
Weaver Architecture
 The drawbacks is the secondary image problem.

RFIC Design
Channel permutation
 (a) Allowing A for nonlinearity and high gain for ADC
– However, the first filter suffers from noise and
linearity issue.
 (b) Relax filter noise requirement
– However, requires linear Amp
 (c) Easy to implement filter in digital circuits
– However, require linear and low thermal and
quantization noise ADC

RFIC Design
Digital IF architecture
 Digital IF : Second down-conversion is performed in
the digital circuits.
 Advantages :
– Alleviate DC offset and flicker noise issue
– No IQ phase and gain mismatch issue
 Difficulty : Need high dynamic and high bandwidth
ADC.

RFIC Design
Sampling IF architecture
 Sample and hold action in the ADC also perform the
down-conversion.
 Sampling frequency could be a little lower than IF
frequency.
 Still needs high performance ADC with high speed
and high linearity.

RFIC Design
Subsampling Receiver
 Sampling in the time domain causes periodically
repeated spectrum in the frequency domain.
 Signal then can be down-converted by very low
frequency sampling rate.

RFIC Design
Subsampling Receiver
 Drawback : Subsampling by a factor of m multiplies
the downconverted noise power of the sampling
circuit by a factor of m.

RFIC Design
Direct Conversion Transmitter
 Direct conversion : the transmitted frequency is
equal to the LO frequency.
 Matching network :
– It is to provide a maximum power transferring to
the antenna.
– It also filters out the out-of-band component that
results from the nonlinearity of PA.

RFIC Design
Transmitter Architecture
 Baseband / RF interface
 Quadrature modulation :

RFIC Design
 Baseband pulse shaping

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 Baseband shaping in GMSK system

RFIC Design
Direct Conversion Transmitter
 Drawback : PA generated a “noisy” signal in the
view of the VCO. It corrupting the LO by means of
“injection locking” or “injection pulling”
 Solutions : to move VCO frequency away from PA

RFIC Design
Two-step transmitter
 Advantages:
– Avoid the pulling effect from PA
– Better I/Q matching due to lower frequency
operation.
 Difficulty : Second BPF must reject out-of-band
signal at (w1-w2) up to 50 ~ 60 dB.

RFIC Design
RF transceiver
case studies

RFIC Design
Motorola FM Rx
 Motorola FM Rx

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Philips Pager Rx
 Philips Pager Rx

RFIC Design
Philips DECT Transceiver
 Philips DECT Transceiver

RFIC Design
Lucent GSM Transceiver
 Lucent GSM Transceiver

RFIC Design
Philips GSM Transceiver
 Philips GSM Transceiver

RFIC Design
References
 B. Razavi, “RF Microelectronics,” Upper Saddle
River: Prentice-Hall,1998.

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