This presentation summarizes the design of a power management integrated circuit. It outlines the layout, pre-simulation and post-simulation statistics, problems encountered, and techniques used. The key findings were that altering I/O pad locations, widening power lines, and using three metal layers for VDD/GND improved efficiency from 95.72% to 96.12%. Techniques to reduce parasitic effects and discharge included metal routing at 90 degrees, using an Euler path for digital circuits, separating VDD/GND, and adding shielding/spacing between lines.

1. Power Management Integrated Circuits
- Final Project Presentation -
Presenter: Tsu-Wen Sung
National Chiao Tung University
Aug 21, 2018

2. Outline
Layout Stats Problem Technique

3. Layout

4. Layout
FEEDBACK
VH
VL
VOP
INIT

5. Stats

6. Stats
Specifications Pre-simulation Post-simulation
Output
voltage
1.2 V 1.203 V 1.203 V
Output
current
30 mA 30.08 mA 30.07 mA
Switching
frequency
2.0 MHz 2.003 MHz 1.879 MHz
Total power 36 mW 37.38 mW 37.63 mW
Output
power
36 mW 36.18 mW 36.17 mW
Efficiency 100 %
96.79 % 96.12 %

7. Problem

8. Problem
After
padding
95.72%
Before
padding
96.02%
Further
improvement
96.12%

9. Problem
• Alter the location of I/O pads
• Widen the power lines
• Three layers of metal for VDD/GND

10. Technique
p Floor plan
• Block-driven • Signal-driven
p Metal intersecting
Reduce parasitic capacitance and magnetic effects
Make use of the third coordinate

11. Technique
p Metal 90 degrees routing?
p Layout of digital circuits
• Corona discharge
• power accumulation
• discontinuous impedance
Much worse in high frequency and voltage designs
Like NOR, NAND, using Euler path

12. Technique
p Separate VDD/GND
p Shielding / Spacing
Reduce ground bounce or overshoot resulted from
digital circuits
Shielding sensitive signals by additional gnd lines
More spacing between lines to avoid coupling