Stuart Riley
7 SlideShares 8 Seguidores
Personal Information
Organização/Local de trabalho
Washington United States
Cargo
Engineer experienced in quality improvement
Setor
Technology / Software / Internet
Site
www.slriley.com
Sobre
ASQ Certified Six-Sigma Green Belt Quality (Yield) Engineer and Software Product Manager with over 15 years experience in semiconductor and semiconductor-related companies. Technical & management skills include Six-Sigma lean, organizational improvement, team leadership, consulting, and project management. Over 10 years experience managing projects with various teams of engineers, technicians and software developers. Over 2 years experience in Yield Management (Quality) Consulting.
Marcadores
defect semiconductor die klarf wafer gnuplot map fail stuart l riley fault yield inspection bit-fail caa critical area analysis
Ver mais
  • Documentos
  • Infográficos
Mais recentes Mais populares

Control Charts For Semiconductor Defect Management

Há 14 anos • 1641 Visualizações

How To Set Kill Ratios For Defects

Há 14 anos • 2921 Visualizações

How To Estimate The Number Of Die Escapes Using In Line Defect Data

Há 14 anos • 675 Visualizações

Semiconductor Defect Management Separating The Vital Few From The Trivial Many

Há 14 anos • 2341 Visualizações

How To Translate Bit Fail Correlation Data To Die Kill Ratios May2009

Há 14 anos • 598 Visualizações