MazuV-debug-system is an implement of RISC-V debug module.

1. MazuV-Debug-System
https://github.com/feathertw/MazuV-debug-system
Fea(feathertw@gmail.com)

2. MazuV-Debug-System
● Project
○ https://github.com/feathertw/MazuV-debug-system
● Base on Risc-V debug spec 0.13
○ https://github.com/riscv/riscv-debug-spec
● Demo with PicoRV32 on Lattice Breakout Board
○ https://hackmd.io/AaQbx7X0RCeZTxcaugB9iw?view

3. RiscV Debug Spec

4. Demo Diagram
PC
GDB
OpenOCD
USB
USB
|
UART
FPGA
Lattice Breakout Board
PicoRV32 DM DTM
UART
DMI
interrupt
Debug Mode

5. Prerequisites
● GDB
○ A user-level program in GNU-Toolchain. It's for debug the
program with debug information.
● OpenOCD
○ A user-level program that help GDB to run each debug command
through the corresponding driver.
● Lattice Breakout Board
○ Lattice iCE40HX-8K low cost FPGA Board. Can work with whole
open-source solution, such as yosys, arachne-pnr, icestorm.
● PicoRV32
○ An open-source CPU written by Verilog and base on Risc-V spec.
It's small and only one file, so it'seasy for new learner.

6. Debug System
● DM(Debug Module)
○ The core of the debug system. There are two slave port for
DTM and CPU, and many configurable registers.
○ An Interrupt to make CPU trap into Debug Mode.
● DTM
○ Receive commands from PC through UART and transfer
them to read, write DM registers. (Choosing UART instead
of common JTAGS is because UART-USB device is much
cheaper)
● Debug Mode
○ In this additional CPU mode, actually CPU does not halt, instead, the
CPU keeps run the DM-ROM code and do the commands from
PC(From software view, the CPU is halted).

7. RiscV DM Registers

8. MazuV-Debug-System Implement
● Can do
○ Halt, resume cpu
○ Access general purpose register, and PC
○ Access memory
○ Single step
○ Set software breakpoint
○ Reset and halt at first instruction
● Cannnot do
○ Set hardware breakpoint
○ Set watchpoint
○ …...

9. Issue of MazuV-Debug-System on PicoRV32
● PicoRV32 are not completely match to RiscV spec, such
as no CSR instruction.
● Need independent debug interrupt port
● Walk around single step implementation

10. Thank you