SlideShare uma empresa Scribd logo
Evaluation of Computer
performance
Dr. Prasenjit Dey
Performance
 The performance of a computer is defined by its speed of
processing of the instructions
 Faster the machine, better the performance
 What are the factors influences the performance of a
computer?
Performance Metrics
 Response Time
 The total time required by an instruction to complete
 From start time of the instruction to the finish time
 It is also known as elapsed time
 Response time = Memory access time + waiting time + CPU
time
 Throughput:
 Number of instructions completed in a specific time
Execution Time
 CPU time
 It is the time when an instruction utilizes the CPU
 Time duration when an instruction is in running state
 It is also known as execution time
 time spent to execute the lines of codes in a program
 CPU time = user CPU time + system CPU time
 elapsed time = user CPU time + system CPU time + waiting time
 Computer performance is measured on the basis of CPU time
Comparison of Performance
 The performance of a machine is inversely proportional to
the CPU time
 Performance = 1/CPU time
 If machine A is n times faster than machine B then
 Performance(A)/performance(B) = n
Clock Cycles
 CPU time is measured with the help of CPU cycles
 Each instruction uses a certain number of CPU cycles to execute an
instruction
 The time taken by an instruction is
 (number of CPU cycles) x (time to execute 1 CPU cycle)
 If all instructions take equal number of cycles then,
 The time required to execute a program of N instructions is
 N x (number of CPU cycle) x (time to execute 1 CPU cycle)
 Avg. program execution time
 (cycles/program) x (seconds/cycle)
 seconds/cycle  cycle time
 Clock rate/frequency  cycle/seconds, used more often
Performance of a Program
 CPU execution time of a program is
 (No. of CPU cycles) x (cycle time)
 (No. of CPU cycles)/(clock rate)
 An efficient program should require less number of CPU
cycles and/or high clock rate
 clock rate  1 Hz. = 1 cycle/sec,
 If clock rate = 200 Mhz?
 Time to execute a program = 1/(200*106) = 5*10-3*10-6 =
5*10-9 sec
Performance of a Program
 In computer, different instructions use different amounts of
CPU cycles
 Bitwise instructions require less number of CPU cycles,
whereas multiplicative instructions, floating point instructions
require more number of CPU cycles,
 To compute the execution time of a program, one should
compute the avg. CPU cycle time or clock rate
CPI: Cycles Per Instruction
 For a given program
 Compute number of instructions
 Compute total number of cycles to execute all instructions
 Divide total number of cycles by number of instructions
 cycles per instruction (CPI)
 The avg. amount of time required to execute an instruction in a
program
 Measured in terms of MIPS (millions of instructions per second)
CPU Execution Time
 CPU execution time of a program is
 N x ( 𝐢=𝟏
𝐍
𝐜𝐲𝐜𝐥𝐞 𝐭𝐢𝐦𝐞 𝐟𝐨𝐫 𝐢𝐧𝐬𝐭𝐫𝐜𝐭𝐢𝐨𝐧 𝐢)/N x cycle time,
 Here N is the total number of instructions in a program
 Average CPI x instruction count x cycle time
 (Average CPI x instruction count) / clock rate
Problem 1
 Let there are 2 machines, machine A and machine B, which
execute the sample program. Where,
 Machine A clock cycle is 10ns and CPI is 2
 Machine B clock cycle is 20ns and CPI is 1.2
 Which one has better performance?
 Computation for machine A
 Avg. CPI x clock cycle time = 2 x 10 = 20ns
 Computation for machine B
 Avg. CPI x clock cycle time = 1.2 x 20 = 24ns
 Machine A has better performance for this program
Problem 2
 Let us consider that two programs that contain three different
types of instructions: type A, type B, and type C
 Type A, type B, and type C instructions require 4, 3, 5 cycles
respectively.
 Suppose program 1, uses 1 type A instructions, 2 type B
instructions, and 2 type C instructions
 Suppose program 2, uses 1 type A instructions, 4 type B
instructions, and 1 type C instructions
 Then which program is faster?
 Computation for program 1
 1*4 + 2*3 + 2*5 = 20cycles
 Computation for program 2
 1*4 + 4*3 + 1*5 = 21cycles
 Program is 1 faster
Problem 3
 Suppose your program consists of 2500 instructions. The
proportion of different kinds of instructions in the program is as
follow: Data transfer instruction 50%, arithmetic instruction 30%
and branching related instructions 20%. The cycles consumed by
these types of instructions are 2, 5, and 10 respectively. What will
be the execution time for a 4 GHz processor to execute your
program?
 Avg CPI = 0.5*2 + 0.3*5 + 0.2*10 = 4.5
 Avg execution time = 2500* (4.5/4 *106 )Sec
= 2500*1.125 *10-6 Sec
= 2.8125ms
Amdahl's Law
 It computes the overall performance enhancement when the
performance of a fraction of code(program) is enhanced
 Overall performance enhancement 
 Overall Speedup = old execution time/new execution time
=
1
(1 – fraction_enhanced) + fraction_enhanced
speedup
 Fraction_enhanced
 The sub part of the code/program which has been enhanced by using
some hardware or compiler
 Speedup
 The performance gain in the enhanced fraction of code
Amdahl's Law: example
 Let a program contains 10 multiplicative instructions and 10
additive instructions. Each multiplicative instruction takes 50ns and
each additive instructions take 10ns.
 Now by adding some hardware, we enhanced the performance of
multiplicative instructions and complete a multiplicative instructions
in 20ns.
 What will be the overall speedup?
 Old execution time = 50*10 + 10*10 =600ns
 New execution time =
1
(1 – fraction_enhanced) + fraction_enhanced
speedup
=
1
1−
500
600
+
500
600
500
200
=
1
1
6
+(
1
3
)
=
1
3
6
=
3
6
= 2
Problems on Amdahl's Law
 With the use of Amdahl’s law, conclude among the given options
which possible improvement is the best one
 Possible improvement
A. Branch CPI can be decreased from 4 to 3
B. Increase clock frequency from 2 to 2.3GHz
C. Store CPI can be decreased from 3 to 2
Instruction type Frequency CPI
ALU 40% 1
Branch 20% 4
Load 30% 2
Store 10% 3
Solution
 Avg. CPI = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*3) = 2.1
 Clock rate = 2GHz
 Avg. instruction execution time = Avg. CPI/clock rate = 2.1/2 =
1.05*10-6 sec
 Case A
 Current execution time = (0.4*1 + 0.2*3 + 0.3*2 + 0.1*3)/2 = 0.95*10-6 sec
 Case B
 Increase clock frequency from 2 to 2.3
 Current execution time = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*3)/(2.3) = 0.91*10-6 sec
 Case C
 Current execution time = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*2)/2 = 1*10-6 sec
Conclusion
 Performance of a machine measured with the help of
clock cycles
 Each instructions require different clock cycles, need
to compute average clock cycle per instruction(CPI)
 Overall performance gain can be achieved by
enhancing a fraction of a program
Thank you

Mais conteúdo relacionado

Mais procurados

parallel programming models
 parallel programming models parallel programming models
parallel programming models
Swetha S
 
deadlock avoidance
deadlock avoidancedeadlock avoidance
deadlock avoidance
wahab13
 
Digital to analog conversion
Digital to analog conversionDigital to analog conversion
Digital to analog conversion
WaseemKhan00
 
General register organization (computer organization)
General register organization  (computer organization)General register organization  (computer organization)
General register organization (computer organization)
rishi ram khanal
 
Computer architecture control unit
Computer architecture control unitComputer architecture control unit
Computer architecture control unit
Mazin Alwaaly
 
Control Units : Microprogrammed and Hardwired:control unit
Control Units : Microprogrammed and Hardwired:control unitControl Units : Microprogrammed and Hardwired:control unit
Control Units : Microprogrammed and Hardwired:control unit
abdosaidgkv
 
Addressing sequencing
Addressing sequencingAddressing sequencing
Addressing sequencing
rajshreemuthiah
 
Data and signals
Data and signalsData and signals
Data and signals
HamzahMohammed4
 
Limitations of memory system performance
Limitations of memory system performanceLimitations of memory system performance
Limitations of memory system performance
Syed Zaid Irshad
 
advanced computer architesture-conditions of parallelism
advanced computer architesture-conditions of parallelismadvanced computer architesture-conditions of parallelism
advanced computer architesture-conditions of parallelism
Pankaj Kumar Jain
 
Floating point arithmetic operations (1)
Floating point arithmetic operations (1)Floating point arithmetic operations (1)
Floating point arithmetic operations (1)
cs19club
 
Round Robin Algorithm.pptx
Round Robin Algorithm.pptxRound Robin Algorithm.pptx
Round Robin Algorithm.pptx
Sanad Bhowmik
 
System calls
System callsSystem calls
System calls
Bernard Senam
 
Boolean algebra
Boolean algebraBoolean algebra
Boolean algebra
Manish Kumar
 
Physical Layer Numericals - Data Communication & Networking
Physical Layer  Numericals - Data Communication & NetworkingPhysical Layer  Numericals - Data Communication & Networking
Physical Layer Numericals - Data Communication & Networking
Drishti Bhalla
 
Cpu Scheduling Galvin
Cpu Scheduling GalvinCpu Scheduling Galvin
Cpu Scheduling Galvin
Sonali Chauhan
 
Memory management
Memory managementMemory management
Memory management
Vishal Singh
 
Error detection correction (CRC)
Error detection correction  (CRC)Error detection correction  (CRC)
Error detection correction (CRC)
Karam Munir Butt
 
Advanced computer architechture -Memory Hierarchies and its Properties and Type
Advanced computer architechture -Memory Hierarchies and its Properties and TypeAdvanced computer architechture -Memory Hierarchies and its Properties and Type
Advanced computer architechture -Memory Hierarchies and its Properties and Type
LalfakawmaKh
 
Addition and subtraction with signed magnitude data (mano
Addition and subtraction with signed magnitude data (manoAddition and subtraction with signed magnitude data (mano
Addition and subtraction with signed magnitude data (mano
cs19club
 

Mais procurados (20)

parallel programming models
 parallel programming models parallel programming models
parallel programming models
 
deadlock avoidance
deadlock avoidancedeadlock avoidance
deadlock avoidance
 
Digital to analog conversion
Digital to analog conversionDigital to analog conversion
Digital to analog conversion
 
General register organization (computer organization)
General register organization  (computer organization)General register organization  (computer organization)
General register organization (computer organization)
 
Computer architecture control unit
Computer architecture control unitComputer architecture control unit
Computer architecture control unit
 
Control Units : Microprogrammed and Hardwired:control unit
Control Units : Microprogrammed and Hardwired:control unitControl Units : Microprogrammed and Hardwired:control unit
Control Units : Microprogrammed and Hardwired:control unit
 
Addressing sequencing
Addressing sequencingAddressing sequencing
Addressing sequencing
 
Data and signals
Data and signalsData and signals
Data and signals
 
Limitations of memory system performance
Limitations of memory system performanceLimitations of memory system performance
Limitations of memory system performance
 
advanced computer architesture-conditions of parallelism
advanced computer architesture-conditions of parallelismadvanced computer architesture-conditions of parallelism
advanced computer architesture-conditions of parallelism
 
Floating point arithmetic operations (1)
Floating point arithmetic operations (1)Floating point arithmetic operations (1)
Floating point arithmetic operations (1)
 
Round Robin Algorithm.pptx
Round Robin Algorithm.pptxRound Robin Algorithm.pptx
Round Robin Algorithm.pptx
 
System calls
System callsSystem calls
System calls
 
Boolean algebra
Boolean algebraBoolean algebra
Boolean algebra
 
Physical Layer Numericals - Data Communication & Networking
Physical Layer  Numericals - Data Communication & NetworkingPhysical Layer  Numericals - Data Communication & Networking
Physical Layer Numericals - Data Communication & Networking
 
Cpu Scheduling Galvin
Cpu Scheduling GalvinCpu Scheduling Galvin
Cpu Scheduling Galvin
 
Memory management
Memory managementMemory management
Memory management
 
Error detection correction (CRC)
Error detection correction  (CRC)Error detection correction  (CRC)
Error detection correction (CRC)
 
Advanced computer architechture -Memory Hierarchies and its Properties and Type
Advanced computer architechture -Memory Hierarchies and its Properties and TypeAdvanced computer architechture -Memory Hierarchies and its Properties and Type
Advanced computer architechture -Memory Hierarchies and its Properties and Type
 
Addition and subtraction with signed magnitude data (mano
Addition and subtraction with signed magnitude data (manoAddition and subtraction with signed magnitude data (mano
Addition and subtraction with signed magnitude data (mano
 

Semelhante a Evaluation of computer performance

Kiến trúc máy tính-COE 301 - Performance.ppt
Kiến trúc máy tính-COE 301 - Performance.pptKiến trúc máy tính-COE 301 - Performance.ppt
Kiến trúc máy tính-COE 301 - Performance.ppt
TriTrang4
 
COMPUTER ARCHITECTURE BASIC CONCEPT
COMPUTER ARCHITECTURE BASIC CONCEPTCOMPUTER ARCHITECTURE BASIC CONCEPT
COMPUTER ARCHITECTURE BASIC CONCEPT
Azizul Mamun
 
L07_performance and cost in advanced hardware- computer architecture.pptx
L07_performance and cost in advanced hardware- computer architecture.pptxL07_performance and cost in advanced hardware- computer architecture.pptx
L07_performance and cost in advanced hardware- computer architecture.pptx
Isaac383415
 
Measuring Performance by Irfanullah
Measuring Performance by IrfanullahMeasuring Performance by Irfanullah
Measuring Performance by Irfanullah
guest2e9811e
 
Computer architecture short note (version 8)
Computer architecture short note (version 8)Computer architecture short note (version 8)
Computer architecture short note (version 8)
Nimmi Weeraddana
 
Cpu performance matrix
Cpu performance matrixCpu performance matrix
Cpu performance matrix
Rehman baig
 
Performance of processor.ppt
Performance of processor.pptPerformance of processor.ppt
Performance of processor.ppt
nivedita murugan
 
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- PerformanceLec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
Hsien-Hsin Sean Lee, Ph.D.
 
Measuringperformance 090527015748-phpapp01
Measuringperformance 090527015748-phpapp01Measuringperformance 090527015748-phpapp01
Measuringperformance 090527015748-phpapp01
manishajadhav13j
 
performance evaluation of parallel processors.pptx
performance evaluation of parallel processors.pptxperformance evaluation of parallel processors.pptx
performance evaluation of parallel processors.pptx
nivedita murugan
 
performance uploading.pptx
performance uploading.pptxperformance uploading.pptx
performance uploading.pptx
SanthiS10
 
Computer Architecture Performance and Energy
Computer Architecture Performance and EnergyComputer Architecture Performance and Energy
Computer Architecture Performance and Energy
Jason J Pulikkottil
 
Parallel Computing - Lec 6
Parallel Computing - Lec 6Parallel Computing - Lec 6
Parallel Computing - Lec 6
Shah Zaib
 
04 performance
04 performance04 performance
04 performance
marangburu42
 
Introduction_pipeline24.ppt which include
Introduction_pipeline24.ppt which includeIntroduction_pipeline24.ppt which include
Introduction_pipeline24.ppt which include
GauravDaware2
 
Lecture 3
Lecture 3Lecture 3
Lecture 3
Mr SMAK
 
Performance analysis(Time & Space Complexity)
Performance analysis(Time & Space Complexity)Performance analysis(Time & Space Complexity)
Performance analysis(Time & Space Complexity)
swapnac12
 
02 performance
02 performance02 performance
02 performance
marangburu42
 
performance
performanceperformance
performance
manogallery
 
Document 14 (6).pdf
Document 14 (6).pdfDocument 14 (6).pdf
Document 14 (6).pdf
RajMantry
 

Semelhante a Evaluation of computer performance (20)

Kiến trúc máy tính-COE 301 - Performance.ppt
Kiến trúc máy tính-COE 301 - Performance.pptKiến trúc máy tính-COE 301 - Performance.ppt
Kiến trúc máy tính-COE 301 - Performance.ppt
 
COMPUTER ARCHITECTURE BASIC CONCEPT
COMPUTER ARCHITECTURE BASIC CONCEPTCOMPUTER ARCHITECTURE BASIC CONCEPT
COMPUTER ARCHITECTURE BASIC CONCEPT
 
L07_performance and cost in advanced hardware- computer architecture.pptx
L07_performance and cost in advanced hardware- computer architecture.pptxL07_performance and cost in advanced hardware- computer architecture.pptx
L07_performance and cost in advanced hardware- computer architecture.pptx
 
Measuring Performance by Irfanullah
Measuring Performance by IrfanullahMeasuring Performance by Irfanullah
Measuring Performance by Irfanullah
 
Computer architecture short note (version 8)
Computer architecture short note (version 8)Computer architecture short note (version 8)
Computer architecture short note (version 8)
 
Cpu performance matrix
Cpu performance matrixCpu performance matrix
Cpu performance matrix
 
Performance of processor.ppt
Performance of processor.pptPerformance of processor.ppt
Performance of processor.ppt
 
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- PerformanceLec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
Lec3 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Performance
 
Measuringperformance 090527015748-phpapp01
Measuringperformance 090527015748-phpapp01Measuringperformance 090527015748-phpapp01
Measuringperformance 090527015748-phpapp01
 
performance evaluation of parallel processors.pptx
performance evaluation of parallel processors.pptxperformance evaluation of parallel processors.pptx
performance evaluation of parallel processors.pptx
 
performance uploading.pptx
performance uploading.pptxperformance uploading.pptx
performance uploading.pptx
 
Computer Architecture Performance and Energy
Computer Architecture Performance and EnergyComputer Architecture Performance and Energy
Computer Architecture Performance and Energy
 
Parallel Computing - Lec 6
Parallel Computing - Lec 6Parallel Computing - Lec 6
Parallel Computing - Lec 6
 
04 performance
04 performance04 performance
04 performance
 
Introduction_pipeline24.ppt which include
Introduction_pipeline24.ppt which includeIntroduction_pipeline24.ppt which include
Introduction_pipeline24.ppt which include
 
Lecture 3
Lecture 3Lecture 3
Lecture 3
 
Performance analysis(Time & Space Complexity)
Performance analysis(Time & Space Complexity)Performance analysis(Time & Space Complexity)
Performance analysis(Time & Space Complexity)
 
02 performance
02 performance02 performance
02 performance
 
performance
performanceperformance
performance
 
Document 14 (6).pdf
Document 14 (6).pdfDocument 14 (6).pdf
Document 14 (6).pdf
 

Mais de Prasenjit Dey

Dynamic interconnection networks
Dynamic interconnection networksDynamic interconnection networks
Dynamic interconnection networks
Prasenjit Dey
 
Machine Learning in Agriculture Module 6: classification
Machine Learning in Agriculture Module 6: classificationMachine Learning in Agriculture Module 6: classification
Machine Learning in Agriculture Module 6: classification
Prasenjit Dey
 
Machine Learning in Agriculture Module 3: linear regression
Machine Learning in Agriculture Module 3: linear regressionMachine Learning in Agriculture Module 3: linear regression
Machine Learning in Agriculture Module 3: linear regression
Prasenjit Dey
 
Machine learning in agriculture module 2
Machine learning in agriculture module 2Machine learning in agriculture module 2
Machine learning in agriculture module 2
Prasenjit Dey
 
Machine Learning in Agriculture Module 1
Machine Learning in Agriculture Module 1Machine Learning in Agriculture Module 1
Machine Learning in Agriculture Module 1
Prasenjit Dey
 
Support vector machine
Support vector machineSupport vector machine
Support vector machine
Prasenjit Dey
 
Numerical on general pipelines
Numerical on general pipelinesNumerical on general pipelines
Numerical on general pipelines
Prasenjit Dey
 
General pipeline concepts
General pipeline conceptsGeneral pipeline concepts
General pipeline concepts
Prasenjit Dey
 
Instruction Set Architecture: MIPS
Instruction Set Architecture: MIPSInstruction Set Architecture: MIPS
Instruction Set Architecture: MIPS
Prasenjit Dey
 
Page replacement and thrashing
Page replacement and thrashingPage replacement and thrashing
Page replacement and thrashing
Prasenjit Dey
 
Addressing mode
Addressing modeAddressing mode
Addressing mode
Prasenjit Dey
 
Register transfer and microoperations part 2
Register transfer and microoperations part 2Register transfer and microoperations part 2
Register transfer and microoperations part 2
Prasenjit Dey
 
Instruction set (prasenjit dey)
Instruction set (prasenjit dey)Instruction set (prasenjit dey)
Instruction set (prasenjit dey)
Prasenjit Dey
 
Register transfer and microoperations part 1
Register transfer and microoperations part 1Register transfer and microoperations part 1
Register transfer and microoperations part 1
Prasenjit Dey
 
Different types of memory and hardware designs of RAM and ROM
Different types of memory and hardware designs of RAM and ROMDifferent types of memory and hardware designs of RAM and ROM
Different types of memory and hardware designs of RAM and ROM
Prasenjit Dey
 
Cache memory
Cache  memoryCache  memory
Cache memory
Prasenjit Dey
 
Carry look ahead adder
Carry look ahead adder Carry look ahead adder
Carry look ahead adder
Prasenjit Dey
 
Binary division restoration and non restoration algorithm
Binary division restoration and non restoration algorithmBinary division restoration and non restoration algorithm
Binary division restoration and non restoration algorithm
Prasenjit Dey
 
Booth's algorithm
Booth's algorithm Booth's algorithm
Booth's algorithm
Prasenjit Dey
 
Computer organization basics and number systems
Computer organization basics and number systemsComputer organization basics and number systems
Computer organization basics and number systems
Prasenjit Dey
 

Mais de Prasenjit Dey (20)

Dynamic interconnection networks
Dynamic interconnection networksDynamic interconnection networks
Dynamic interconnection networks
 
Machine Learning in Agriculture Module 6: classification
Machine Learning in Agriculture Module 6: classificationMachine Learning in Agriculture Module 6: classification
Machine Learning in Agriculture Module 6: classification
 
Machine Learning in Agriculture Module 3: linear regression
Machine Learning in Agriculture Module 3: linear regressionMachine Learning in Agriculture Module 3: linear regression
Machine Learning in Agriculture Module 3: linear regression
 
Machine learning in agriculture module 2
Machine learning in agriculture module 2Machine learning in agriculture module 2
Machine learning in agriculture module 2
 
Machine Learning in Agriculture Module 1
Machine Learning in Agriculture Module 1Machine Learning in Agriculture Module 1
Machine Learning in Agriculture Module 1
 
Support vector machine
Support vector machineSupport vector machine
Support vector machine
 
Numerical on general pipelines
Numerical on general pipelinesNumerical on general pipelines
Numerical on general pipelines
 
General pipeline concepts
General pipeline conceptsGeneral pipeline concepts
General pipeline concepts
 
Instruction Set Architecture: MIPS
Instruction Set Architecture: MIPSInstruction Set Architecture: MIPS
Instruction Set Architecture: MIPS
 
Page replacement and thrashing
Page replacement and thrashingPage replacement and thrashing
Page replacement and thrashing
 
Addressing mode
Addressing modeAddressing mode
Addressing mode
 
Register transfer and microoperations part 2
Register transfer and microoperations part 2Register transfer and microoperations part 2
Register transfer and microoperations part 2
 
Instruction set (prasenjit dey)
Instruction set (prasenjit dey)Instruction set (prasenjit dey)
Instruction set (prasenjit dey)
 
Register transfer and microoperations part 1
Register transfer and microoperations part 1Register transfer and microoperations part 1
Register transfer and microoperations part 1
 
Different types of memory and hardware designs of RAM and ROM
Different types of memory and hardware designs of RAM and ROMDifferent types of memory and hardware designs of RAM and ROM
Different types of memory and hardware designs of RAM and ROM
 
Cache memory
Cache  memoryCache  memory
Cache memory
 
Carry look ahead adder
Carry look ahead adder Carry look ahead adder
Carry look ahead adder
 
Binary division restoration and non restoration algorithm
Binary division restoration and non restoration algorithmBinary division restoration and non restoration algorithm
Binary division restoration and non restoration algorithm
 
Booth's algorithm
Booth's algorithm Booth's algorithm
Booth's algorithm
 
Computer organization basics and number systems
Computer organization basics and number systemsComputer organization basics and number systems
Computer organization basics and number systems
 

Último

How to Manage Your Lost Opportunities in Odoo 17 CRM
How to Manage Your Lost Opportunities in Odoo 17 CRMHow to Manage Your Lost Opportunities in Odoo 17 CRM
How to Manage Your Lost Opportunities in Odoo 17 CRM
Celine George
 
Cognitive Development Adolescence Psychology
Cognitive Development Adolescence PsychologyCognitive Development Adolescence Psychology
Cognitive Development Adolescence Psychology
paigestewart1632
 
Hindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdfHindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdf
Dr. Mulla Adam Ali
 
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
National Information Standards Organization (NISO)
 
Digital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental DesignDigital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental Design
amberjdewit93
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE”           .MARY JANE WILSON, A “BOA MÃE”           .
MARY JANE WILSON, A “BOA MÃE” .
Colégio Santa Teresinha
 
How to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint  Presentations.pptxHow to deliver Powerpoint  Presentations.pptx
How to deliver Powerpoint Presentations.pptx
HajraNaeem15
 
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective UpskillingYour Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Excellence Foundation for South Sudan
 
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UPLAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
RAHUL
 
The basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptxThe basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptx
heathfieldcps1
 
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
GeorgeMilliken2
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
WaniBasim
 
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem studentsRHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
Himanshu Rai
 
UGC NET Exam Paper 1- Unit 1:Teaching Aptitude
UGC NET Exam Paper 1- Unit 1:Teaching AptitudeUGC NET Exam Paper 1- Unit 1:Teaching Aptitude
UGC NET Exam Paper 1- Unit 1:Teaching Aptitude
S. Raj Kumar
 
PIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf IslamabadPIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf Islamabad
AyyanKhan40
 
Leveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit InnovationLeveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit Innovation
TechSoup
 
A Independência da América Espanhola LAPBOOK.pdf
A Independência da América Espanhola LAPBOOK.pdfA Independência da América Espanhola LAPBOOK.pdf
A Independência da América Espanhola LAPBOOK.pdf
Jean Carlos Nunes Paixão
 
South African Journal of Science: Writing with integrity workshop (2024)
South African Journal of Science: Writing with integrity workshop (2024)South African Journal of Science: Writing with integrity workshop (2024)
South African Journal of Science: Writing with integrity workshop (2024)
Academy of Science of South Africa
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
Priyankaranawat4
 
Main Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docxMain Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docx
adhitya5119
 

Último (20)

How to Manage Your Lost Opportunities in Odoo 17 CRM
How to Manage Your Lost Opportunities in Odoo 17 CRMHow to Manage Your Lost Opportunities in Odoo 17 CRM
How to Manage Your Lost Opportunities in Odoo 17 CRM
 
Cognitive Development Adolescence Psychology
Cognitive Development Adolescence PsychologyCognitive Development Adolescence Psychology
Cognitive Development Adolescence Psychology
 
Hindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdfHindi varnamala | hindi alphabet PPT.pdf
Hindi varnamala | hindi alphabet PPT.pdf
 
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
Pollock and Snow "DEIA in the Scholarly Landscape, Session One: Setting Expec...
 
Digital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental DesignDigital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental Design
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE”           .MARY JANE WILSON, A “BOA MÃE”           .
MARY JANE WILSON, A “BOA MÃE” .
 
How to deliver Powerpoint Presentations.pptx
How to deliver Powerpoint  Presentations.pptxHow to deliver Powerpoint  Presentations.pptx
How to deliver Powerpoint Presentations.pptx
 
Your Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective UpskillingYour Skill Boost Masterclass: Strategies for Effective Upskilling
Your Skill Boost Masterclass: Strategies for Effective Upskilling
 
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UPLAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
LAND USE LAND COVER AND NDVI OF MIRZAPUR DISTRICT, UP
 
The basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptxThe basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptx
 
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
What is Digital Literacy? A guest blog from Andy McLaughlin, University of Ab...
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
 
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem studentsRHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
RHEOLOGY Physical pharmaceutics-II notes for B.pharm 4th sem students
 
UGC NET Exam Paper 1- Unit 1:Teaching Aptitude
UGC NET Exam Paper 1- Unit 1:Teaching AptitudeUGC NET Exam Paper 1- Unit 1:Teaching Aptitude
UGC NET Exam Paper 1- Unit 1:Teaching Aptitude
 
PIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf IslamabadPIMS Job Advertisement 2024.pdf Islamabad
PIMS Job Advertisement 2024.pdf Islamabad
 
Leveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit InnovationLeveraging Generative AI to Drive Nonprofit Innovation
Leveraging Generative AI to Drive Nonprofit Innovation
 
A Independência da América Espanhola LAPBOOK.pdf
A Independência da América Espanhola LAPBOOK.pdfA Independência da América Espanhola LAPBOOK.pdf
A Independência da América Espanhola LAPBOOK.pdf
 
South African Journal of Science: Writing with integrity workshop (2024)
South African Journal of Science: Writing with integrity workshop (2024)South African Journal of Science: Writing with integrity workshop (2024)
South African Journal of Science: Writing with integrity workshop (2024)
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
 
Main Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docxMain Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docx
 

Evaluation of computer performance

  • 2. Performance  The performance of a computer is defined by its speed of processing of the instructions  Faster the machine, better the performance  What are the factors influences the performance of a computer?
  • 3. Performance Metrics  Response Time  The total time required by an instruction to complete  From start time of the instruction to the finish time  It is also known as elapsed time  Response time = Memory access time + waiting time + CPU time  Throughput:  Number of instructions completed in a specific time
  • 4. Execution Time  CPU time  It is the time when an instruction utilizes the CPU  Time duration when an instruction is in running state  It is also known as execution time  time spent to execute the lines of codes in a program  CPU time = user CPU time + system CPU time  elapsed time = user CPU time + system CPU time + waiting time  Computer performance is measured on the basis of CPU time
  • 5. Comparison of Performance  The performance of a machine is inversely proportional to the CPU time  Performance = 1/CPU time  If machine A is n times faster than machine B then  Performance(A)/performance(B) = n
  • 6. Clock Cycles  CPU time is measured with the help of CPU cycles  Each instruction uses a certain number of CPU cycles to execute an instruction  The time taken by an instruction is  (number of CPU cycles) x (time to execute 1 CPU cycle)  If all instructions take equal number of cycles then,  The time required to execute a program of N instructions is  N x (number of CPU cycle) x (time to execute 1 CPU cycle)  Avg. program execution time  (cycles/program) x (seconds/cycle)  seconds/cycle  cycle time  Clock rate/frequency  cycle/seconds, used more often
  • 7. Performance of a Program  CPU execution time of a program is  (No. of CPU cycles) x (cycle time)  (No. of CPU cycles)/(clock rate)  An efficient program should require less number of CPU cycles and/or high clock rate  clock rate  1 Hz. = 1 cycle/sec,  If clock rate = 200 Mhz?  Time to execute a program = 1/(200*106) = 5*10-3*10-6 = 5*10-9 sec
  • 8. Performance of a Program  In computer, different instructions use different amounts of CPU cycles  Bitwise instructions require less number of CPU cycles, whereas multiplicative instructions, floating point instructions require more number of CPU cycles,  To compute the execution time of a program, one should compute the avg. CPU cycle time or clock rate
  • 9. CPI: Cycles Per Instruction  For a given program  Compute number of instructions  Compute total number of cycles to execute all instructions  Divide total number of cycles by number of instructions  cycles per instruction (CPI)  The avg. amount of time required to execute an instruction in a program  Measured in terms of MIPS (millions of instructions per second)
  • 10. CPU Execution Time  CPU execution time of a program is  N x ( 𝐢=𝟏 𝐍 𝐜𝐲𝐜𝐥𝐞 𝐭𝐢𝐦𝐞 𝐟𝐨𝐫 𝐢𝐧𝐬𝐭𝐫𝐜𝐭𝐢𝐨𝐧 𝐢)/N x cycle time,  Here N is the total number of instructions in a program  Average CPI x instruction count x cycle time  (Average CPI x instruction count) / clock rate
  • 11. Problem 1  Let there are 2 machines, machine A and machine B, which execute the sample program. Where,  Machine A clock cycle is 10ns and CPI is 2  Machine B clock cycle is 20ns and CPI is 1.2  Which one has better performance?  Computation for machine A  Avg. CPI x clock cycle time = 2 x 10 = 20ns  Computation for machine B  Avg. CPI x clock cycle time = 1.2 x 20 = 24ns  Machine A has better performance for this program
  • 12. Problem 2  Let us consider that two programs that contain three different types of instructions: type A, type B, and type C  Type A, type B, and type C instructions require 4, 3, 5 cycles respectively.  Suppose program 1, uses 1 type A instructions, 2 type B instructions, and 2 type C instructions  Suppose program 2, uses 1 type A instructions, 4 type B instructions, and 1 type C instructions  Then which program is faster?  Computation for program 1  1*4 + 2*3 + 2*5 = 20cycles  Computation for program 2  1*4 + 4*3 + 1*5 = 21cycles  Program is 1 faster
  • 13. Problem 3  Suppose your program consists of 2500 instructions. The proportion of different kinds of instructions in the program is as follow: Data transfer instruction 50%, arithmetic instruction 30% and branching related instructions 20%. The cycles consumed by these types of instructions are 2, 5, and 10 respectively. What will be the execution time for a 4 GHz processor to execute your program?  Avg CPI = 0.5*2 + 0.3*5 + 0.2*10 = 4.5  Avg execution time = 2500* (4.5/4 *106 )Sec = 2500*1.125 *10-6 Sec = 2.8125ms
  • 14. Amdahl's Law  It computes the overall performance enhancement when the performance of a fraction of code(program) is enhanced  Overall performance enhancement   Overall Speedup = old execution time/new execution time = 1 (1 – fraction_enhanced) + fraction_enhanced speedup  Fraction_enhanced  The sub part of the code/program which has been enhanced by using some hardware or compiler  Speedup  The performance gain in the enhanced fraction of code
  • 15. Amdahl's Law: example  Let a program contains 10 multiplicative instructions and 10 additive instructions. Each multiplicative instruction takes 50ns and each additive instructions take 10ns.  Now by adding some hardware, we enhanced the performance of multiplicative instructions and complete a multiplicative instructions in 20ns.  What will be the overall speedup?  Old execution time = 50*10 + 10*10 =600ns  New execution time = 1 (1 – fraction_enhanced) + fraction_enhanced speedup = 1 1− 500 600 + 500 600 500 200 = 1 1 6 +( 1 3 ) = 1 3 6 = 3 6 = 2
  • 16. Problems on Amdahl's Law  With the use of Amdahl’s law, conclude among the given options which possible improvement is the best one  Possible improvement A. Branch CPI can be decreased from 4 to 3 B. Increase clock frequency from 2 to 2.3GHz C. Store CPI can be decreased from 3 to 2 Instruction type Frequency CPI ALU 40% 1 Branch 20% 4 Load 30% 2 Store 10% 3
  • 17. Solution  Avg. CPI = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*3) = 2.1  Clock rate = 2GHz  Avg. instruction execution time = Avg. CPI/clock rate = 2.1/2 = 1.05*10-6 sec  Case A  Current execution time = (0.4*1 + 0.2*3 + 0.3*2 + 0.1*3)/2 = 0.95*10-6 sec  Case B  Increase clock frequency from 2 to 2.3  Current execution time = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*3)/(2.3) = 0.91*10-6 sec  Case C  Current execution time = (0.4*1 + 0.2*4 + 0.3*2 + 0.1*2)/2 = 1*10-6 sec
  • 18. Conclusion  Performance of a machine measured with the help of clock cycles  Each instructions require different clock cycles, need to compute average clock cycle per instruction(CPI)  Overall performance gain can be achieved by enhancing a fraction of a program