7. ARM S3C4510B 7
1 ARM
1.1 ARM Advanced RISC Machines
ARM Advanced RISC Machines
1990 ARM ARM
IP ARM
ARM
32 RISC 75 ARM
ARM RISC
ARM ARM
ARM
ARM ARM
1.2 ARM
1.2.1 ARM
ARM
1 32 RISC ARM
ARM
8. ARM S3C4510B 8
8 /16
2 85% ARM ARM
3 ARM ADSL
ARM DSP
4 ARM
5 ARM
32 SIM ARM
ARM
1.2.2 ARM
RISC ARM
1
2 Thumb 16 /ARM 32
3
4
5
6
1.3 ARM
ARM ARM
ARM ARM
ARM7
ARM9
ARM9E
ARM10E
ARM11
SecurCore
Inter StrongARM Xscale
ARM7 ARM9 ARM9E ARM10 4
SecurCore
9. ARM S3C4510B 9
1.3.1 ARM7
ARM7 32 RISC
ARM7
ICE RT
0.9MIPS/MHz 3
16 Thumb
Windows CE Linux Palm OS
ARM9 ARM9E ARM10E
130MIPS
ARM7 Internet
ARM7 ARM7TDMI ARM7TDMI-S
ARM720T ARM7EJ ARM7TDMI 32 RISC
ARM TDMI
T 16 Thumb
D Debug
M Multiplier
I ICE
Samsung S3C4510B
1.3.2 ARM9
ARM9
5
1.1MIPS/MHz
32 ARM 16 Thumb
32 AMBA
MMU Windows CE Linux Palm OS
MPU
Cache Cache
ARM9
10. ARM S3C4510B 10
ARM9 ARM920T ARM922T ARM940T
1.3.3 ARM9E
ARM9E DSP
Java ARM9E
DSP DSP
ARM9E
DSP
5
32 ARM 16 Thumb
32 AMBA
VFP9
MMU Windows CE Linux Palm OS
MPU
Cache Cache
300MIPS
ARM9
ARM9E ARM926EJ-S ARM946E-S ARM966E-S
1.3.4 ARM10E
ARM10E
ARM9 50 ARM10E
ARM10E
DSP
6
32 ARM 16 Thumb
64 AMBA
VFP10
MMU Windows CE Linux Palm OS
Cache Cache
400MIPS
11. ARM S3C4510B 11
/
ARM10E
ARM10E ARM1020E ARM1022E ARM1026EJ-S
1.3.5 ARM11
ARM 2003 4 29 ARM CPU ARM11
Jaguar ARM11
ARM11 0.13 350MHz 500MHz
533 750MHz 0.10 1GHz
ARM7 ARM9 400MHz
Intel Xscale 500MHz
1.3.6 SecurCore
SecurCore 32 RISC
SecurCore ARM
SecurCore ARM
SecurCore
SecurCore SecurCore SC100 SecurCore SC110 SecurCore SC200
SecurCore SC210
1.3.7 StrongARM Xscale
Intel StrongARM SA-1100 ARM 32 RISC
Inter ARM
ARMv4 Intel
Intel StrongARM
StrongARM
Xscale ARMv5TE
12. ARM S3C4510B 12
16 Thumb DSP
Intel 2006 Xscale
Xscale
1.4 ARM
1.4.1 RISC
CISC Complex Instruction Set Computer
CISC
20 80 80
20
1979 RISC Reduced
Instruction Set Computer RISC
RISC
RISC RISC
2 3
/
ARM
/
CISC RISC RISC
CISC RISC CISC
CPU CISC RISC CPU
13. ARM S3C4510B 13
RISC CISC CPU
1.4.2 ARM
ARM 37 32
31 PC 32
6 CPU 32
ARM 7
15
R0 R14 1 2 7
ARM
1.4.3 ARM
ARM ARM Thumb
ARM 32 Thumb 16 Thumb ARM
ARM 30 40
32
ARM
1.5 ARM
ARM ARM
ARM
ARM
ARM
ARM
Windows CE Linux
ARM720T MMU Memory Management Unit ARM
ARM720T ARM920T ARM922T ARM946T Xscale MMU ARM7TDMI
MMU Windows CE Linux uCLinux RTLinux uC/OSII
14. ARM S3C4510B 14
MMU ARM7TDMI
MMU
S3C4510B MMU ARM
uCLinux RTLinux uC/OSII MMU
ARM ARM7
0.9MIPS/MHz ARM7 20MHz 133MHz
ARM9 1.1MIPS/MHz ARM9
150MHz 233MHz ARM10 750MHz
ARM
ARM9 ARM10 ARM7 ARM7
ARM7
ARM
ATMEL AT91F40162 2MB
ARM ARM
USB IIS LCD
RTC ADC DAC DSP
ARM
ARM
ARM
Samsung Atmel TI Intel Cirrus Logic Motorola
ARM
25. ARM S3C4510B 25
2-2 M[4 0]
M[4 0]
0b10000 PC CPSR,R0-R14
0b10001 FIQ PC CPSR, SPSR_fiq R14_fiq-R8_fiq, R7 R0
0b10010 IRQ PC CPSR, SPSR_irq R14_irq,R13_irq,R12 R0
0b10011 PC CPSR, SPSR_svc R14_svc,R13_svc,,R12 R0,
0b10111 PC CPSR, SPSR_abt R14_abt,R13_abt, R12 R0,
0b11011 PC CPSR, SPSR_und R14_und,R13_und, R12 R0,
0b11111 PC CPSR ARM v4 , R14 R0
2-2
2.6 Exceptions
26. ARM S3C4510B 26
2.6.1 ARM
2-3 ARM
ARM
SWI
IRQ CPSR I 0 IRQ
FIQ CPSR F 0 FIQ
2.6.2
R14_<Exception_Mode> = Return Link
SPSR_<Exception_Mode> = CPSR
27. ARM S3C4510B 27
CPSR[4:0] = Exception Mode Number
CPSR[5] = 0 ARM
If <Exception_Mode> == Reset or FIQ then
FIQ FIQ
CPSR[6] = 1
CPSR[7] = 1
PC = Exception Vector Address
2.6.3
2.6.4
SUBS PC,R14_fiq ,#4
R14_fiq 4 PC
SPSR_mode CPSR
SUBS PC , R14_irq , #4
R14_irq 4 PC
SPSR_mode CPSR
28. ARM S3C4510B 28
SUBS PC, R14_abt, #4
SUBS PC, R14_abt, #8
MOV PC , R14_svc
MOVS PC, R14_und
2.6.5 /
2-4 R14 PC
2-4 /
ARM R14_x Thumb R14_x
BL MOV PC R14 PC 4 PC 2 1
SWI MOVS PC R14_svc PC 4 PC 2 1
29. ARM S3C4510B 29
UDEF MOVS PC R14_und PC 4 PC 2 1
FIQ SUBS PC R14_fiq 4 PC 4 PC 4 2
IRQ SUBS PC R14_irq 4 PC 4 PC 4 2
PABT SUBS PC R14_abt 4 PC 4 PC 4 1
DABT SUBS PC R14_abt 8 PC 8 PC 8 3
RESET NA 4
1 PC BL/SWI/
2 PC FIQ IRQ
3 PC
4 R14_svc
2.6.6 Exception Vectors
2-5
0x0000,0000
0x0000,0004
0x0000,0008
0x0000,000C
0x0000,0010
0x0000,0014
0x0000,0018 IRQ IRQ
0x0000,001C FIQ FIQ
2.6.7 Exception Priorities
2-6
1
2
3 FIQ
4 IRQ
5
6 SWI
30. ARM S3C4510B 30
2.6.8
ARM
ARM
PC
2.7
ARM
ARM
ARM
Banked 8/16 X86
31. ARM S3C4510B 31
3 ARM
3.1 ARM
3.1.1 ARM
3-1 ARM
ADC
ADD
AND
B
BIC
BL
BLX
BX
CDP
CMN
CMP
EOR
LDC
32. ARM S3C4510B 32
LDM
LDR
MCR ARM
MLA
MOV
MRC ARM
MRS CPSR SPSR
MSR CPSR SPSR
MUL 32
MLA 32
MVN
ORR
RSB
RSC
SBC
STC
STM
STR
SUB
SWI
SWP
TEQ
TST
3.1.2
ARM CPSR
ARM 4 4 [31:28] 16
B EQ BEQ CPSR Z
16 15 3-2 16 1111
3-2
0000 EQ Z
0001 NE Z
0010 CS C
33. ARM S3C4510B 33
0011 CC C
0100 MI N
0101 PL N
0110 VS V
0111 VC V
1000 HI C Z
1001 LS C Z
1010 GE N V
1011 LT N V
1100 GT Z N V
1101 LE Z N V
1110 AL
3.2 ARM
ARM
3.2.1
ADD R0 R0 1 R0
ADD R0 R0 0x3f R0
0x &
3.2.2
ADD R0 R1 R2 R0
R1 R2 R0
3.2.3
35. ARM S3C4510B 35
BL
BL NEXT NEXT
3.2.7
First In Last Out FILO
Full Stack
Empty Stack
Ascending Stack
Decending Stack
ARM
3.3 ARM
ARM
3.3.1
ARM
PC
PC 4GB
MOV LR PC
36. ARM S3C4510B 36
4GB
ARM 32MB
4
B
B Label Label
CMP R1 0 CPSR Z Label
BEQ Label
BL Label Label PC
R14
37. ARM S3C4510B 37
3.3.2
MOV R1 R0 R0 R1
MOV PC R14 R14 PC
MOV R1 R0 LSL 3 R0 3 R1
49. ARM S3C4510B 49
LSR
0 31
MOV R0, R1, LSR#2 R1 R0
ASR
31 0 31
MOV R0, R1, ASR#2 R1 R0 31
ROR
0 31 32
MOV R0, R1, ROR#2 R1 R0
RRX
C
0 31
MOV R0, R1, RRX#2 R1 R0
3.3.9
ARM 16
ARM
ARM ARM ARM
ARM ARM
50. ARM S3C4510B 50
ARM 5
CDP P3 2 C12 C10 C3 4 P3
LDC P3 C4 [R0] ARM R0
P3 C4
STC P3 C4 [R0] P3 C4 ARM
R0
51. ARM S3C4510B 51
MCR P3 3 R0 C4 C5 6 ARM R0
P3 C4 C5
MRC P3 3 R0 C4 C5 6 P3 ARM
3.3.10
ARM
SWI 0x02 02
52. ARM S3C4510B 52
3.4 Thumb
ARM 32 ARM 16
Thumb Thumb ARM 16
32 Thumb 32
Thumb ARM Thumb ARM
Thumb ARM
ARM ARM ARM
Thumb ARM Thumb
ARM Thumb 32
32 Thumb 16 ARM
Thumb ARM
Thumb
Thumb 16 ARM
Thumb ARM
Thumb ARM
ARM Thumb
32 ARM 16
Thumb
3.5
ARM
X86
ARM
Thumb ARM ARM
Thumb ARM
53. ARM S3C4510B 53
4 ARM
4.1 ARM
ARM
ARM
4.1.1
Symbol Definition ARM
GBLA GBLL GBLS
LCLA LCLL LCLS
SETA SETL SETS
RLIST
GBLA GBLL GBLS
GBLA GBLL GBLS ARM
57. ARM S3C4510B 57
DCQ DCQU
DataTest DCQ 100
SPACE
SPACE 0
SPACE
DataSpace SPACE 100 100 0
MAP { }
MAP MAP
MAP FIELD
MAP 0x100 R0 0x100 R0
FIELD
FIELD FILED #
FIELD MAP MAP
FIELD
MAP FIELD
MAP 0x100 0x100
A FIELD 16 A 16 0x100
B FIELD 32 B 32 0x110
S FIELD 256 S 256 0x130
4.1.3
Assembly Control
58. ARM S3C4510B 58
IF ELSE ENDIF
WHILE WEND
MACRO MEND
MEXIT
IF
1
ELSE
2
ENDIF
IF ELSE ENDIF IF
1 2 ELSE
2 IF 1
IF ELSE ENDIF
GBLL Test Test
IF Test = TRUE
1
ELSE
2
ENDIF
WHILE
WEND
WHILE WEND
WHILE
WHILE WEND
GBLA Counter Counter
WHILE Counter < 10
59. ARM S3C4510B 59
WEND
$ $ 1 $ 2
MEND
MACRO MEND
$
MACRO MEND
MACRO MEND
MEXIT
MEXIT
4.1.4
AREA
ALIGN
CODE16 CODE32
ENTRY
END
EQU
EXPORT GLOBAL
IMPORT
EXTERN
GET INCLUDE
INCBIN
60. ARM S3C4510B 60
RN
ROUT
AREA 1 2
AREA
| |1_test|
CODE READONLY
DATA READWRITE
READONLY READONLY
READWRITE READWRITE
ALIGN ALIGN ELF
0 31
2
COMMON
COMMON
AREA Init CODE READONLY
Init
ALIGN { { }}
ALIGN |
2 1 2 4 8 16
2
AREA Init CODE READONLY ALIEN 3 8
END
CODE16 CODE32
61. ARM S3C4510B 61
CODE16 16 Thumb
CODE32 32 ARM
ARM Thumb CODE16
16 Thumb CODE32
32 ARM ARM Thumb
AREA Init CODE READONLY
CODE32 32 ARM
LDR R0 NEXT 1 R0
BX R0 Thumb
16 Thumb
ENTRY
ENTRY
ENTRY ENTRY
ENTRY
AREA Init CODE READONLY
ENTRY
END
END
AREA Init CODE READONLY
END
EQU { }
62. ARM S3C4510B 62
EQU C
define EQU *
EQU 32
CODE16 CODE32 DATA
Test EQU 50 Test 50
Addr EQU 0x55 CODE32 Addr 0x55 32 ARM
EXPORT {[WEAK]}
EXPORT
EXPORT GLOBAL [WEAK]
AREA Init CODE READONLY
END
IMPORT {[WEAK]}
IMPORT
[WEAK]
0 B BL
B BL NOP
AREA Init CODE READONLY
END
EXTERN {[WEAK]}
EXTERN
63. ARM S3C4510B 63
[WEAK]
0 B BL
B BL NOP
AREA Init CODE READONLY
END
GET
GET
INCLUDE GET
EQU
MAP FIELD GET
C include
GET INCBIN
AREA Init CODE READONLY
END
INCBIN
INCBIN
AREA Init CODE READONLY
END
RN
RN
64. ARM S3C4510B 64
{ } ROUT
ROUT
AREA ROUT ROUT
ROUT
4.2
ARM Thumb
{ } { } { }
4.2.1
ARM Thumb
ARM Thumb GBLA GBLL GBLS
LCLA LCLL LCLS SETA SETL
65. ARM S3C4510B 65
SETS
ARM Thumb
32 0 232-1
-231 231-1
$
$
$
$
$ $
4.2.2
/ MOD
X Y
X Y X Y
66. ARM S3C4510B 66
X Y X Y
X Y X Y
X/Y X Y
X MOD Y X Y
ROL ROR SHL SHR
X Y
X ROL Y X Y
X ROR Y X Y
X SHL Y X Y
X SHR Y X Y
AND OR NOT EOR
X Y
X AND Y X Y
X OR Y X Y
NOT Y Y
X EOR Y X Y
= > < >= <= /= <>
X Y
X=Y X Y
X>Y X Y
X<Y X Y
X >= Y X Y
X <= Y X Y
X /= Y X Y
X <> Y X Y
LAND LOR LNOT LEOR
X Y
X LAND Y X Y
X LOR Y X Y
LNOT Y Y
X LEOR Y X Y
512
LEN
67. ARM S3C4510B 67
LEN X
LEN X
CHR
CHR 0 255 M
CHR M
STR
STR
STR STR
T F
STR X
X
LEFT
LEFT
X LEFT Y
X Y
RIGHT
LEFT RIGHT
X RIGHT Y
X Y
CC
CC
X CC Y
X 1 Y 2 CC Y X
PC
BASE
BASE
BASE X
X
INDEX
INDEX
INDEX X
X
68. ARM S3C4510B 68
?X
X
DEF
DEF
DEF X
X
4.3
4.3.1
ARM Thumb
AREA Init CODE READONLY
ENTRY
Start
LDR R0 =0x3FF5000
LDR R1 0xFF
STR R1 [R0]
LDR R0 =0x3FF5008
LDR R1 0x01
STR R1 [R0]
...
END
AREA
Init ENTRY
END
69. ARM S3C4510B 69
END
4.3.2
ARM BL
BL
LR
PC
LR PC
R0 R3
BL
AREA Init CODE READONLY
ENTRY
Start
LDR R0 =0x3FF5000
LDR R1 0xFF
STR R1 [R0]
LDR R0 =0x3FF5008
LDR R1 0x01
STR R1 [R0]
BL PRINT_TEXT
PRINT_TEXT
...
END
4.3.3
S3C4510B S3C4510B
;***************************************************************************
;Institute of Automation,Chinese Academy of Sciences
;Description: This example shows the UART communication
;Author: Li Juguang
;Date:
;***************************************************************************
;***********************************
;Define Special Function Register
71. ARM S3C4510B 71
LDR R0,=Line1
BL PrintLine
LDR R0,=Line2
BL PrintLine
LDR R0,=Line3
BL PrintLine
LDR R0,=Line4
BL PrintLine
LDR R1,=0x7FFFFF
LOOP1
SUBS R1,R1,#1
BNE LOOP1
B LOOP
;***************************************************
;Print line
;***************************************************
PrintLine
MOV R4,LR
MOV R5,R0
Line
LDRB R1,[R5],#1
AND R0,R1,#&FF
TST R0,#&FF
MOVEQ PC,R4
BL PutByte
B Line
PutByte
LDR R3,=UARTSTAT0
LDR R2,[R3]
TST R2,#&40
BEQ PutByte
LDR R3,=UTXBUF0
STR R0,[R3]
MOV PC,LR
Line1 DCB &A,&D,"******************************************************",0
Line2 DCB &A,&D,"Chinese Academy of Sciences,Institute of Automation,Complex
System Lab.",0
Line3 DCB &A,&D," ARM Development Board Based on Samsung ARM S3C4510B.",0
Line4 DCB &A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,&A,&D,0
END
72. ARM S3C4510B 72
4.3.4 C/C++
ARM C/C++
C/C++
C/C++
C/C
C/C
C/C
C/C
C/C C/C
5 6
;*************************************************************************
;Institute of Automation, Chinese Academy of Sciences
;File Name: Init.s
;Description:
;Author: Li Juguang
;Date:
;************************************************************************
IMPORT Main ;
AREA Init,CODE,READONLY
ENTRY
LDR R0,=0x3FF0000 5 6
LDR R1,=0xE7FFFF80
STR R1,[R0]
LDR SP,=0x3FE1000
BL Main Main C/C++
END
Main C/C
Main C
main
/***************************************************************************
* Institute of Automation, Chinese Academy of Sciences
* File Name: main.c
73. ARM S3C4510B 73
* Description: P0,P1 LED flash.
* Author: Li Juguang
* Date:
***************************************************************************/
void Main(void)
{
int i;
*((volatile unsigned long *) 0x3ff5000) = 0x0000000f;
while(1)
{
*((volatile unsigned long *) 0x3ff5008) = 0x00000001;
for(i=0; i<0x7fFFF; i++)
;
*((volatile unsigned long *) 0x3ff5008) = 0x00000002;
for(i=0; i<0x7FFFF; i++)
;
}
}
4.4
74. ARM S3C4510B 74
4.4.1
4.4.2
·
·
AREA Init CODE READONLY
ENTRY
B Reset_Handler ;Reset_Handler
B Undef_Handler
B SWI_Handler
B PreAbort_Handler
B DataAbort_Handler
B . ;
B IRQ_Handler
B FIQ_Handler
Reset_Handler
...
4.4.3
75. ARM S3C4510B 75
ARM 4GB
MB
4GB
ARM
Samsung S3C2410
Remap
Samsung
S3C4510B
ARM
Flash SDRAM
PC
0x0 0x0 Flash ROM
0x0 Flash RAM
Flash
RAM
0x0 0x0 Flash
PC
Flash Flash
78. ARM S3C4510B 78
ARM ARM Thumb
Thumb Thumb
4.4.8
4.4.9 C
IMPORT C_Entry main
B C_Entry
ARM ADS C
IMPORT __main
B __main
__main( ) C
main( ) main( )
main( )
main( ) main( )
main( )
4.5
85. ARM S3C4510B 85
—
5.2.2 S3C4510B
5-1 S3C4510B
XCLK 80 I CLKSEN
PLL S3C4510B
86. ARM S3C4510B 86
CLKSEN XCLK S3C4510B
MCLKO/SDCLK 77 O SDCLK SDRAM
CLKSEL 83 I CLKSEL PLL
S3C4510B CLKSEL
XCLK S3C4510B
nRESET 82 I ESET S3C4510B
nRESET 64
CLKOEN 76 I
TMODE 63 I
FILTER 55 AI PLL 820pF
TCK 58 I JTAG
TMS 59 I S3C4510B JTAG
TDI 60 I JTAG
S3C4510B
TDO 61 O JTAG
S3C4510B
nTRST 62 I JTAG
ADDR[21:0]/ 117-110 O 22 ROM/ SRAM
ADDR[10]/AP 129-120 FLASH DRAM I/O 4M
135-132 16M
XDATA[31:0] 141-136 I/O S3C4510B 8
154-144 16 32
166-159
175-169
nRAS[3:0]/ 94,91, O S3C4510B 4 DRAM
nSDCS[3:0] 90,89 nRAS nSDCS[3:0] SDRAM
nCAS[3:0] 98,97, O DRAM 4
nCAS[0] 96,95 nCAS nSDRAS
/nSDRAS SDRAM nSDCAS SDRAM
nCAS[1] CKE SDRAM
/nSDCAS
87. ARM S3C4510B 87
nCAS[2]/CKE
nDWE 99 O DRAM
nWBE[3:0] ROM/SRAM/FLASH
nECS[3:0] 70,69, O 4 I/O
68,67 I/O 16KB nECS
I/O
nEWAIT 71 I I/O ,
nRCS[5:0] 88-84,75 O S3C4510B 6
ROM/SRAM/FLASH
B0SIZE[1:0] 74,73 I
ROM/SRAM/FLASH 0
01 8 10 16 11
32 00
nOE 72 O
nWBE[3:0]/ 107, O
DQM[3:0] 102-100 DRAM DRAM
nCAS[3:0] nDWE DQM SDRAM
/
ExtMREQ 108 I
S3C4510B
ExtMACK S3C4510B
ExtMACK 109 O
MDC 50 O MDIO
MDIO 48 I/O
PHY
LITTLE 49 I S3C4510B
S3C4510B
COL/COL_10M 38 I
TX_CLK/ 46 I S3C4510B TX_CLK
TXCLK_10M TXD[3:0] TX_EN MII PHY
TX_CLK TXD[3:0] TX_EN
TXCLK_10M 10M PHY
88. ARM S3C4510B 88
TXD[3:0] 44,43, O TXD[3:0]
LOOP_10M 40,39 TXD_10M 10M PHY
TXD_10M LOOP_10M
TX_EN/ 47 O
TXEN_10M
TX_ERR/ 45 O
PCOMP_10M
CRS/CRS_10M 28 I
RX_CLK/ 37 I RX_CLK
RXCLK_10M 25MHz 100M
2.5MHz 10M
RXCLK_10M 10M PHY
RXD[3:0] 35 34 I
RXD_10M 33 30
RX_DV/ 29 I
LINK10M
RX_ERR 36 I
TXDA 9 O
RXDA 7 I
nDTRA 6 O nDTRA
nRTSA 8 O
nCTSA 10 I
nDCDA 13 I
nSYNCA 15 O
RXCA 14 I
TXCA 16 I/O
TXDB 20 O
RXDB 18 I
nDTRB 17 O
nRTSB 19 O
nCTSB 23 I
nDCDB 24 I
nSYNCB 26 O
RXCB 25 I
TXCB 27 I/O
UCLK 64 I UART
UART
UARXD0 202 I
UATXD0 204 O
90. ARM S3C4510B 90
131
156
168
178 198
VSSI 12 32 GND
52 66
104
143
158
188 208
VDDA 53 Power
VSSA 54 GND
5.2.3 CPU Special Function Registers
S3C4510B CPU ARM 32 ARM7TDMI
5.4 ARM7TDMI RISC Reduced Instruction Set
Computer CISC Complex Instruction Set Computer RISC
ARM7TDMI ARM7
Thumb ARM 36 32 ARM
16
Thumb ARM
Thumb 16 32 ARM
ARM 32 ARM 16 Thumb
Thumb 16 32
ARM7TDMI 32 ARM 16 Thumb
Thumb ARM
ARM Thumb
101. ARM S3C4510B 101
8 A21-A0 4M
16 A22-A1 4M
32 A23-A2 4M
S3C4510B
S3C4510B
S3C4510B
S3C4510B
5-6
A-1 A
DRAM A-2
General DMA1 GDMA1 A-3
General DMA0 GDMA0 A-4
B HDLC B A-5
A HDLC A A-6
MAC DMA BDMA A-7 A
B-1 B
B-2 B
102. ARM S3C4510B 102
S3C4510B A B
S3C4510B
ExtMREQs CPU ExtMACK
S3C4510B
S3C4510B DRAM
DRAM
3. Control Register
SYSCFG
SRAM
64KB 5.5
SYSCFG DRAM
SRAM
SYSCFG
SYSCFG 0x0000 / 0x67FFFF91
0
1 Cache
1
8KB Cache SRAM
00 = 4KB SRAM 4KB Cache
01 = 0KB SRAM 8KB Cache
10 = 8KB SRAM 0KB Cache
10 CE
103. ARM S3C4510B 103
16 SRAM
16
00001=S3C4510X KS32C50100
11001=S3C4510B
0 4 DRAM /EDO DRAM
1 4 DRAM SDRAM
0x3FF0000 SYSCFG
64MB
0x3FF0000
ROMCON 0x3014 ROMCON
0x3FF0000 0x3014 0x3FF3014
0x3000000 ROMCON
0x3003014
0x3FF0000
SYSCFG CE Cache Cache
Cache
8KB SRAM SYSCFG[5 4] Cache 8KB
Cache SRAM SRAM
S3C4510B 4
CPU 4
ARM7TDMI
4. MUX (System clock and MUX Bus Control
Register)
104. ARM S3C4510B 104
EXTDBWTH
EXTDBWTH 0x3010 / 0x00000000
114. ARM S3C4510B 114
5-11 HY29LV160
A[19:0] I
DQ[15]/A[-1] I/O 8 16
DQ[14:0] DQ[15]/A[-1] 21 DQ[14:8]
BYTE# I
CE# I
OE# I
WE# I
RESET# I
RY/BY# O
VCC -- 3.3V
VSS --
