Create your first VHDL model for simple logic circuits Skills gained: 1- Know the basic structure of a VHDL model (entity, architecture) 2- Model simple combinational logic This is part of VHDL 360 course

1. VHDL 360© by: Mohamed Samy Samer El-Saadany

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3. Module 1 Create your first model for a simple logic circuit

4. Objective Create your first VHDL model for simple logic circuits Skills gained: Know the basic structure of a VHDL model (entity, architecture) Model simple combinational logic VHDL 360 © 4

6. With-Select

7. When-ElseVHDL 360 © 5

8. VHDL Design Units After understanding our first model*, let’s move forward & understand how to construct one 6 VHDL 360 © *Module 0: Introduction to VHDL

9. VHDL Design Units A VHDL Model (Design unit) consists of: Entity Define ports (inputs and outputs) Architecture Define operation (input/output relation) VHDL 360 © 7

10. Entity Description entity <entity_name> is port ( <port_name> : <mode> <type>; <port_name> : <mode> <type>; … -- last port has no semicolon <port_name> : <mode> <type> ); Endentity; 8 VHDL 360 © <mode>: port direction IN: Input that can only be read OUT: Output that can only be written to INOUT: Input or output can be read and written to Syntax: Example: ENTITY model1 IS--VHDL is case insensitive PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic); END model1 ;

11. Entity Description 9 VHDL 360 © Bit values: ‘0’ --Binary Zero ‘1’ -- Binary One Std_logic values ‘U’ -- Uninitialized ‘X’ -- Forcing Unknown ‘0’ --Forcing Zero ‘1’ -- Forcing One ‘Z’ -- High Impedance ‘W’ -- Weak Unknown ‘L’ -- Weak Zero ‘H’ -- Weak One ‘-’ -- Don’t Care Types: VHDL offers the following standard types: Integer: -231 to 231-1 Bit, Bit_vector … IEEE Packages offer more types: Std_logic, std_logic_vector … Require use of appropriate IEEE packages Example: Using Standard Types Example: Using IEEE Types LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY model1 IS PORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e:OUTstd_logic_vector(7 downto 0)); END model1 ; ENTITY model1 IS PORT( a :INbit_vector(3 downto 0); b :INbit; c :INbit; d :INbit; e :OUTbit); END model1 ;

12. Exercise 1 Write the entity of the following: 1-bit Full Adder 10 VHDL 360 ©

13. Answer of Exercise 1 11 VHDL 360 © LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITYfullAdderIS PORT( In1, In2, CarryIn:INstd_logic; Sum :OUTstd_logic; CarryOut:OUT std_logic); ENDfullAdder;

14. Architecture Description architecture <arch_name> of <entity_name> is -- architecture declarations begin -- architecture body endarchitecture; 12 VHDL 360 © Syntax: A given architecture represents one possible implementation for its associated entity Architecture declaration: defines internal signals, components, types …etc to be used in architecture body Architecture body: defines implementation details of input/output relationship Multiple architectures can exist for each entity Example: Internal signals ARCHITECTURErtlOF model1 IS SIGNAL x :std_logic; SIGNAL y :std_logic; BEGIN x <= a AND b; y <= c AND d; e <= x OR y; ENDrtl; signal <sig_name>: <sig_type>; Concurrent Assignments

15. Architecture Body <target> <= <expression>; 13 VHDL 360 © Architecture body can only contain concurrent statements, in this module we will only focus on Concurrent assignments With-select When-else Concurrent Assignments LHS can be an internal signal or an output port RHS is an expression that operates on internal signal and/or input ports Syntax: Example: ARCHITECTUREexprOF example1 IS SIGNAL u, w, x, y, z :std_logic; SIGNAL a, b, c :integer; BEGIN x <= y AND z;-- logical expression w <=NOT x; u <= w;-- direct assignment c <= a + b;-- arithmetic expression ENDexpr; Arithmetic Operators + , - , * , / Logical Operators NOT AND, NAND OR, NOR XOR, XNOR

16. Internal signals We use Internal Signals for: Internal connections in structural description Intermediate calculations Avoid illegal port usage situations: Read Output port Syntax: architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name>: <sig_type>; begin -- assign to internal signal <sig_name> <= <expression>; -- read the internal signal <sig_name> <= <expression>; endarchitecture; Example: LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY illegal IS PORT( A :INstd_logic; B :INstd_logic; C :INstd_logic; F :OUTstd_logic; G :OUTstd_logic); END illegal ; ARCHITECTUREstructOF illegal IS -- Internal signal declarations SIGNAL sig1 :std_logic; SIGNAL sig2 :std_logic; SIGNAL sig3 :std_logic; BEGIN F <= sig3 AND sig1 AND C; G <= F AND sig1 AND sig2;-- Reading Out port F is illegal sig3 <=NOT(A); sig1 <=NOT(B); sig2 <=NOT(C); ENDstruct; Illegal use of an output port (used as the “and” gate input) 14 VHDL 360 ©

17. Internal signals Example: LIBRARYieee; USEieee.std_logic_1164.all; USEieee.std_logic_arith.all; ENTITY legal IS PORT( A :INstd_logic; B :INstd_logic; C :INstd_logic; F :OUTstd_logic; G :OUTstd_logic); END legal ; ARCHITECTUREstructOF legal IS -- Internal signal declarations SIGNAL sig1 :std_logic; SIGNAL sig2 :std_logic; SIGNAL sig3 :std_logic; SIGNAL sig4 :std_logic; BEGIN sig4 <= sig3 AND sig1 AND C; -- using internal signal sig4 G <= sig4 AND sig1 AND sig2; F <= sig4; sig3 <=NOT(A); sig1 <=NOT(B); sig2 <=NOT(C); ENDstruct; Internal Signals used for intermediate relations 15 VHDL 360 ©

18. Expressions & Operators 16 VHDL 360 © Each operator is defined for specific data type(s) Arithmetic operators are defined for standard integer types Logical operators are defined for the standard bit, bit_vector types Logical & arithmetic operators are defined for std_logic & std_logic_vector types in IEEE std_logic_* packages  You need to use the appropriate package before applying an operator on a type Example: ARCHITECTUREstructOFexprIS -- Internal signal declarations SIGNAL x, y, z :integer; BEGIN -- Operators can be chained to form complex expressions F <= C AND (NOT(B)) AND (NOT(A)); -- parentheses control association of operators and operands -- use parentheses for readability G <= (COR (NOT(A)))XOR(NOT(B) AND(BNORC)); Z <= X + Y; -- using addition operator defined for integer type ENDstruct;

19. Operators* 17 VHDL 360 © *More operator will be presented throughout the course

20. Operators 18 VHDL 360 © Example: -- Library & package used for architecture scope LIBRARY ieee; USE ieee.std_logic_unsigned.all; -- Need to use unsigned arithmetic operators ARCHITECTUREexprOF example1 IS SIGNAL u, w :std_logic_vector(3 downto 0); SIGNAL a :integer; BEGIN -- Adding an integer to an std_logic_vector returning std_logic_vector u <= w + a; ENDexpr; Where’s the Carry Out?!

21. Exercise 2 Write the architecture of the following: 1-bit Full Adder 19 VHDL 360 ©

22. Answer of Exercise 2 20 VHDL 360 © LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITYfullAdderIS PORT( In1, In2, CarryIn:INstd_logic; Sum :OUTstd_logic; CarryOut:OUT std_logic); ENDfullAdder; ARCHITECTUREexprOFfullAdderIS signal temp :std_logic; BEGIN temp <=In1 XOR In2; Sum <= temp XORCarryIn; CarryOut<= (In1 AND In2) OR (CarryInAND temp); ENDexpr;

23. 21 VHDL 360 © a b F c d Sel(1:0) Architecture Body With-Select <select_signal> can be an internal signal or an input port <target> can be an internal signal or an output port <value> constants representing one of possible <select_signal> values. “When others” is a must if not all values of <select_signal> are covered Syntax: With <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, …. < expression> whenothers; Example: Architecture behave ofmux_withis Begin Withselselect F <= a when"00", b when"01", c when"10", d whenothers; -- needed to cover missing “sel” values EndArchitecture;

24. 22 VHDL 360 © a b F c d Sel(1:0) Architecture Body When-else LHS can be an internal signal or an output port RHS is an expression that operates on internal signal and/or input ports when the branch condition is true Last “else” branch covers all missing conditions Syntax: <target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else<expression> ; Example: Architecture behave ofmux_whenis Begin F <= a whensel="00"else b whensel="01"else c whensel="10"else d;-- This is one statement with semicolon at the end only EndArchitecture;

25. Exercise 3 a F 2 4 F a 4 2 Write the entity and architecture of the following (using with-select then using when-else): 2x4 Decoder 4x2 Encoder Encoder4x2 Decoder2x4 23 VHDL 360 ©

26. Decoder 2x4(with-select) a F 2 4 libraryIEEE; useIEEE.std_logic_1164.all; entity decoder2x4 is port(a:instd_logic_vector(1downto0); F:outstd_logic_vector(3downto0)); endentity; Architecture behave of decoder2x4 is Begin with A select F <="0001"when"00", "0010"when"01", "0100"when"10", "1000" when others; EndArchitecture; 24 VHDL 360 ©

27. Decoder 2x4 (when-else) a F 2 4 libraryIEEE; useIEEE.std_logic_1164.all; entity decoder2x4 is port(a:instd_logic_vector(1downto0); F:outstd_logic_vector(3downto0)); endentity; Architecture behave of decoder2x4 is Begin F <="0001" when a ="00"else "0010"when a ="01"else "0100" when a ="10"else "1000"; EndArchitecture; 25 VHDL 360 ©

28. Encoder4x2 (with-select) F a 2 4 libraryIEEE; useIEEE.std_logic_1164.all; entity encoder4x2 is port(a:instd_logic_vector(3downto0); F:outstd_logic_vector(1downto0)); endentity; Architecture behave of encoder4x2 is Begin With a select F <="00"when"0001", "01"when"0010", "10"when"0100", "11"whenothers; EndArchitecture; 26 VHDL 360 ©

29. Next Module Module 2: Writing more complex Models VHDL 360 © 27

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