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Introduction to 8086 Microprocessor Presented by- Rajvir Singh
8086 Microprocessor ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
8086 Internal Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],8086 CPU Bus Interface  Unit (BIU) Execution Unit (EU)
Bus Interface Unit ,[object Object],[object Object],[object Object],[object Object],[object Object]
Execution Unit ,[object Object],[object Object],[object Object]
Architecture Diagram of 8086
CONTROL  SYSTEM ARITHMETIC LOGIC UNIT FLAGS Instruction Queue OPERANDS ∑ Memory Interface EU BIU Instruction Decoder DESTINATION INDEX (DI) SOURCE INDEX (SI) BASE POINTER (BP) STACK POINTER (SP) DL DH CL CH BL BH AL AH EXTRA SEGMENT (ES) INSTRUCTION POINTER (IP) DATA SEGMENT (DS) STACK SEGMENT (SS) CODE SEGMENT (CS) 6 5 4 3 2 1
Execution Unit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Instruction Decoder ,[object Object],Control System ,[object Object],Arithmetic Logic Unit ,[object Object]
General Purpose Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],DL DH CL CH BL BH AL AH DL CL BL AL DX DH CX CH BX BH AX AH
Flag Register ,[object Object],[object Object],[object Object],[object Object],[object Object]
Flag Register CF U PF U AF U ZF SF TF IF DF OF U U U U DIRECTION FLAG DF 9. INTERRUPT FLAG IF 8. Control Flags TRAP FLAG TF 7. OVERFLOW FLAG OF 6. SIGN FLAG SF 5. ZERO FLAG ZF 4. AUXILIARY CARRY AF 3. PARITY FLAG PF 2. Conditional Flags (Compatible with 8085, except OF) CARRY FLAG CF 1.
Bus Interface Unit ,[object Object],[object Object],[object Object],[object Object]
CONTROL  SYSTEM ARITHMETIC LOGIC UNIT FLAGS Instruction Queue OPERANDS ∑ Memory Interface EU BIU Instruction Decoder DESTINATION INDEX (DI) SOURCE INDEX (SI) BASE POINTER (BP) STACK POINTER (SP) DL DH CL CH BL BH AL AH EXTRA SEGMENT (ES) INSTRUCTION POINTER (IP) DATA SEGMENT (DS) STACK SEGMENT (SS) CODE SEGMENT (CS) 6 5 4 3 2 1
Instruction Queue ,[object Object],[object Object],[object Object],[object Object],[object Object]
Pipelining ,[object Object],[object Object],[object Object]
Memory Segmentation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory 00000H FFFFFH 1MB Address Range 64KB Memory Segment Only 4 such segments can be addressed at a time 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4
Code Segment ,[object Object],Stack Segment ,[object Object],Data & Extra Segments ,[object Object]
Memory 00000H FFFFFH 1MB Address Range Code Segment Stack Segment Data & Extra Segments 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Segment Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory 00000H FFFFFH 1MB Address Range Starting Addresses of Segments 1000 0H 4000 0H 5000 0H F000 0H CS DS ES SS Stack Segment 15 14 13 12 11 10 9 8 7 Extra Segment Data Segment 4 3 Code Segment 1
[object Object],[object Object],[object Object],[object Object],[object Object]
Instruction Pointer (IP) Register ,[object Object],[object Object],[object Object]
Memory 00000H FFFFFH 1MB Address Range 348A  H 4214 H 38AB4 H CS IP Physical Address Start of Code Segment 348A0H Code Byte MOV AL, BL 38AB4H IP = 4214H + 0 Stack Segment 15 14 13 12 11 10 9 8 7 Extra Segment Code Segment 4 3 Data Segment 1
Stack Segment (SS) Register   Stack Pointer (SP) Register ,[object Object],[object Object],[object Object],[object Object]
Other Pointer & Index Registers ,[object Object],[object Object],[object Object],[object Object],[object Object]

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1326 Introduction To 8086 Microprocessor

  • 1. Introduction to 8086 Microprocessor Presented by- Rajvir Singh
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  • 7. CONTROL SYSTEM ARITHMETIC LOGIC UNIT FLAGS Instruction Queue OPERANDS ∑ Memory Interface EU BIU Instruction Decoder DESTINATION INDEX (DI) SOURCE INDEX (SI) BASE POINTER (BP) STACK POINTER (SP) DL DH CL CH BL BH AL AH EXTRA SEGMENT (ES) INSTRUCTION POINTER (IP) DATA SEGMENT (DS) STACK SEGMENT (SS) CODE SEGMENT (CS) 6 5 4 3 2 1
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  • 12. Flag Register CF U PF U AF U ZF SF TF IF DF OF U U U U DIRECTION FLAG DF 9. INTERRUPT FLAG IF 8. Control Flags TRAP FLAG TF 7. OVERFLOW FLAG OF 6. SIGN FLAG SF 5. ZERO FLAG ZF 4. AUXILIARY CARRY AF 3. PARITY FLAG PF 2. Conditional Flags (Compatible with 8085, except OF) CARRY FLAG CF 1.
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  • 14. CONTROL SYSTEM ARITHMETIC LOGIC UNIT FLAGS Instruction Queue OPERANDS ∑ Memory Interface EU BIU Instruction Decoder DESTINATION INDEX (DI) SOURCE INDEX (SI) BASE POINTER (BP) STACK POINTER (SP) DL DH CL CH BL BH AL AH EXTRA SEGMENT (ES) INSTRUCTION POINTER (IP) DATA SEGMENT (DS) STACK SEGMENT (SS) CODE SEGMENT (CS) 6 5 4 3 2 1
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  • 18. Memory 00000H FFFFFH 1MB Address Range 64KB Memory Segment Only 4 such segments can be addressed at a time 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4
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  • 20. Memory 00000H FFFFFH 1MB Address Range Code Segment Stack Segment Data & Extra Segments 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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  • 22. Memory 00000H FFFFFH 1MB Address Range Starting Addresses of Segments 1000 0H 4000 0H 5000 0H F000 0H CS DS ES SS Stack Segment 15 14 13 12 11 10 9 8 7 Extra Segment Data Segment 4 3 Code Segment 1
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  • 25. Memory 00000H FFFFFH 1MB Address Range 348A H 4214 H 38AB4 H CS IP Physical Address Start of Code Segment 348A0H Code Byte MOV AL, BL 38AB4H IP = 4214H + 0 Stack Segment 15 14 13 12 11 10 9 8 7 Extra Segment Code Segment 4 3 Data Segment 1
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