2. 3D-IC stacking is a promising technique for
miniaturization and performance
enhancement of electronic systems
The adoption of advanced packaging technologies could change
the industry food chain of the semiconductor.
•
Today wire bonding is limited in density and performances and
Flip Chip cannot be used for chip stacking.
3D Stacked Die with Thermal Interconnects technology seems
to be unavoidable in the future for miniaturization first, and
increased performance and cost later.
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6. Semiconductor packaging houses
gain from more device complexity
Increased I/O density on chips, power/performance requirements, yield/cost
requirements and form factor constraints (mobile) are coming to push
increased use of 3D technology. This trend benefits the packaging
subcontractors in the semiconductor industry.
Larger packaging subcontractors, like Amkor (AMKR), ASE, and SPIL, will
take market share from smaller sub-contractors. Large packaging houses like
Amkor have invested in 3D packaging technologies, such as through silicon
via (TSV) fabrication, silicon interposers, etc. They are also well-positioned
for an industry shift occurring from wire bonding to 3D.
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7. Why Conductive Adhesive Edge Attach Interconnection?
These novel interconnect systems interconnects provide solutions to
many limitations of current SiP and Chip Stacking methods.
Wire Bonding;
Long Connections
Low Density
RC Delays
High Impedance
High Power consumption
Poor Heat Dissipation
Large Area
Challenging Interposers
I/O Pitch limitations
Conductive Interposer;
Short Connections
Very High Density
No RC Delays
Low Impedance
Low Power Consumption
Excellent Heat Dissipation
Small Connecting Area
No Real I/O Limitations
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8. MicroCoat Technologies High
Thermally Conductive and Non-
Conductive Adhesives Meet the
Challenge for 3D Stacking for;
Cell Phones, Smart Phones, PDAs, Digital Cameras,
Wireless Networking, Game Boxes, Multimedia, etc.
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9. Thermal Management of 3D Stacked
Die Using Conductive Adhesive for
Heat Dissipation
The conductive paths provide an ground-breaking method for helping to
cool the device(s) with the high thermal conductivity of the epoxy
acting as cooling fins. It is shown that a 32MB 3D stacked DRAM cache
can reduce the cycles per memory access of a twothreaded RMS
benchmark on average by 13% and as much as 55% while increasing
the peak temperature by a negligible 0.08ºC. Off-die BW and power are
also reduced by 66% on average. It is also shown that a 3D floorplan of
a high performance microprocessor can simultaneously reduce power
15% and increase performance 15% with a small 14ºC increase in peak
temperature. Voltage scaling can reach neutral thermals with a
simultaneous 34% power reduction and 8% performance improvement.
Bryan Black, et al, Intel Corporation.
MicroCoat Technologies
11. 3D Thermal Management
Using just “any” conductive adhesive will reduce
your opportunity for success.
3-dimensional integrated circuits (3D IC’s) technology places circuit
blocks in the vertical dimension in addition to the conventional horizontal
plane. Compared to conventional planar ICs, 3D ICs have shorter
latencies as well as lower power consumption, due to shorter wires. The
benefits of 3D ICs increase as we stack more die, due to successive
reductions in wire lengths. However, as we stack more die, the power
density increases due to increasing proximity of active (heat generating)
devices, thus causing the temperatures to increase. Also, the topmost die
on the 3D stack are located further from the heat sink and experience a
longer heat dissipation path. Kiran Puttaswamy Georgia Institute of Technology School of
Electrical and Computer Engineering Atlanta, GA & Gabriel H. Loh Georgia Institute of Technology
College of Computing Atlanta, GA
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12. Advantages of SD0802C Over Other 3D
Dispensable Adhesives
Copper Bearing Standard Ag SD0802HTC
REAL Interfacial Thermal
Conductivity W/mK 4-7 2.5 – 4.2 12.0
Weight Loss
on Cure TGA 4% 2.75 – 3.1% .07 - 1.1%
Work Life (Hours) 12 12-48 144 !!
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13. Advantages of SD0802C Over Other 3D
Dispensable Adhesives
Copper material shrinks more on cure that is why it cracks!!
User will have long term failures trying to adhere to either aluminum or
gold IC pads
User will be able to use full 10cc syringes (40 grams) using SD0802 on
JetSpray or Standard Dispense Equipment
If a company is depositing a 200um line and it shrinks 4% that is 8um of
shrinkage. The actual contact resistance between the dispensed copper
material and the pad on the die will be very high and the adhesion will
get progressively worse with temperature cycling
SD0802 has a Cure Temperature Window of 80oC to >150oC
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14. ** Thermal Conductivity vs. thermal impedance in adhesive bondlines.
.
Although some adhesive manufacturers may claim to have bulk thermal
conductivity values higher than 30 W/m°K, device manufacturers need
to appreciate that the bulk value is only an indicator of potential for heat
transfer through the adhesive bondline. The material with the lowest
thermal impedance should actually be the goal, as it is with this that the
best heat transfer can actually be obtained. The factors that affect
thermal impedance include: adhesion at the interface, surface wetting,
thin adhesive bondlines, low shrinkage, and void-free bondlines. If the
interfacial adhesion is weak or impacted by filler alignment or solvent
removal, then the thermal resistance across the interface will be so
great that the bulk resistivity becomes meaningless. If the bondline can
be kept thin, for example by using a solventless adhesive, then heat
transfer will be very efficient regardless of the difference in the bulk
thermal conductivity.
MicroCoat Technologies