Resume for full time jobs

1. SARATH INAMPUDI
Block 683A, #04-97, Woodlands Drive 62, Singapore - 731683
PHONE: 65-68942900 (H), 65-98526450 (M)
sarluke@hotmail.com
http://www.linkedin.com/pub/sarath-inampudi/11/a18/b4a
OBJECTIVE
o Electronics & Instrumentation engineer seeking full time job to pursue quality industrial projects and product development
SUMMARY
o Multidisciplinary educational background, with sound knowledge of electrical/electronics (semiconductor device physics,
process integration, VLSI design), mechanical and instrumentation/control engineering principles
o 2 years of work experience in semiconductor, automotive, medical device and energy (thermal, gas, nuclear) applications
o Well versed with product development life cycle and project management aspects
o Understanding of validation, verification and failure analysis testing procedures
o Rapid learning curve and intangible skill set, including leadership, problem solving, multitasking and facing challenges
o Proven public speaker/presenter possessing excellent oral and written communication skills
o Exposure to multinational cultures (underwent education in India, Malaysia, Singapore and the United States)
EDUCATION
THE UNIVERSITY OF TEXAS AT DALLAS, Texas, USA
December 2008 (GPA: 3.533/4)
Master of Science in Electrical Engineering (Major: Microelectronics – Solid state and system fabrication)
GRE – 1490/1600, TOEFL – 293/300
VELLORE INSTITUTE OF TECHNOLOGY, Tamil Nadu, India (IEE UK accredited)
June 2006 (GPA: 8.88/10)
Bachelor of Technology in Engineering (Major: Electronics and Instrumentation)
Graduated First Class with Honours/Distinction
COMPUTER SKILLS
Programming Languages:
C, C++
Application software:
MS Office, MiniTab statistical suite, MatLab basics
Design and simulation tools:
Intellisuite (MEMS), LabVIEW, Casino E-Beam, Virtual Photonics, SolidWorks, IDEAS, Digital circuit simulation (Cadence,
Synopsis, Verilog, Hspice, AvanWaves), VASP abinitio DFT basics, PLC programming basics
GRADUATE DEGREE COURSES
Quantum physical electronics, Semiconductor processing technology, Nanolithography, Electromagnetic Fields & Waves,
VLSI digital design, Microelectromechanical systems (MEMS), Advanced Electron Microscopy, Computational physics of
nanomaterials, Radio frequency engineering, Optical communication engineering, Independent Research course (One
semester – Dr. Kyeongjae Cho, PhD MIT)

2. WORK AND RESEARCH EXPERIENCE (SEMICONDUCTORS)
Nanoscholar Intern (Texas govt. funded), SEMATECH, Austin, Texas, USA (June 1st, 2007– August 30th, 2007)
Division: Front End Processes (Non – Planar CMOS extension Group)
Manager: Dr. Rusty Harris, Mentor: Dr. Hemant Adhikari
o Cleanroom certification training (Class 1), Wet etching – Si nitride and TEOS layers on sSOI wafers
o Ellipsometry & XRR fab tools - Studied NiSi coated blanket wafers to achieve contact resistance optimization
o Electrical characterization – IdVd, IdVg, CV measurements on 45 nm node FinFETs
o Literature survey and documentation/presentation
- FinFETs with SiGe/Ge fins
- Lithographically defined nanowires (properties/fabrication/performance)
University of Texas at Dallas, USA
Nanostructure Modeling Lab
Advisor: Dr. Kyeongjae Cho, PhD MIT
o Literature survey and documentation/presentation
- Strain engineering, mobility effects and SiNW sensors
- 2D quantum simulator for transport modeling
o VASP DFT simulations to study effect of dopants adsorbed on graphene surface
- Analysis done by considering K and NO2 dopants and calculating changes it brings in the bandstructure and DOS
(compared to undoped pristine grapheme)
ACADEMIC PROJECTS (SEMICONDUCTORS)
o E-beam simulation: Resolution properties (Beam energy, width, thickness) and scattering effects (Pri, Sec and BSE)
o Simulation of multi gate MOSFETs (DG and TG FinFETs) using Matlab (Effect on short channel characteristics)
o Capacitive MEMS accelerometer using Intellisuite: +/- 20g, Static and dynamic analysis (transient vibration modes)
o Traffic signal control system using Verilog, Cadence and Synopsis
- Schematic and layout design with minimum diffusion breaks (D flip flop and logic gates with multiple inputs
using NMOS and PMOS transistors)
- Physical verification (DRC, LVS, parasitic leakages and RCX checks)
- Floor planning (routing/placement) and Pathmill delay analysis
- Output verification/comparison between high level simulation using existing cell libraries and output obtained
using custom-made cell libraries/netlists
o Molecular dynamics and VASP analysis of carbon based structures (Graphite, Diamond and Fullerene buckyball)
o Quantum/atomistic simulations of Si, GaAs, H, C,C2 dimer, graphite and diamond using VASP abinitio DFT tool
(Electronic band structure, DOS and partial DOS, Equilibrium lattice and bulk modulus calculations)
WORK EXPERIENCE (PRODUCT DEVELOPMENT, VALIDATION AND FAILURE ANALYSIS)
Product development engineer (intern), OSTEOMED, Dallas, Texas, USA (April 8th, 2009 – September 23rd, 2009)
Division: Craniomaxillofacial/Neuro group
Manager: Sarah Lewis
o Working with leading OMF surgeons to develop custom-made plates and templates for mandibular angle fractures
- Research mandibular biomechanics and bone density
- Proof of concept, design and technical feasibility analysis of disposable template and pre-bent plate
o Bench testing of screws for analyzing pull-out strength, insertion torque and disengagement torque
o Research palatal expanders, orbital floor fractures and effect on mandibular biomechanics due to dental implants
Graduate student intern, DELPHI, Kokomo, Indiana, USA (February 12th, 2008– August 8th, 2008)
Division: Active Safety
Manager: Ward Everly, Mentor: Kirk McClure
o Designed and built Delphi’s first test fixture for operational validation of the Delphi Camera Module prototype over
automotive temperature range (-40 deg C to 85 deg C), with Modulation Transfer Function as primary measurand
o Performed comprehensive data analysis on the MTF values obtained from the validation modules using MiniTab
o Failure analysis of validation modules using X-ray testing and high power Zeiss optical microscope
o Responsibilities included being the key interface person between camera EE group, Validation group and Optics group
o Took on a leadership role in ensuring DCM ADP Phase I was completed as per schedule, despite unforeseen circumstances
o Overall project expenditure: US$6000
- Achieved total cost saving of US$14000 from sanctioned project budget for validation (US$20000)

3. WORK AND RESEARCH EXPERIENCE (PROCESS CONTROL)
Balmer and Lawrie Corporation Limited, Mumbai, INDIA
Summer intern (May 15th, 2006– June 15th, 2006)
o Divided time between Grease and Barrel divisions
o Analyzed entire process flow to gain firsthand knowledge of industrial sensor applications for automation control
o Chemical and operational validation testing of grease samples using various ISO recommended testing procedures
Bhabha Atomic Research Centre (BARC), Mumbai, INDIA
Reactor Control Division
Undergraduate Senior Design Project, Dec 1st, 2005 – July 15th, 2006
Advisor: Dr. A.P.Tiwari (Scientific Officer – G)
o “Self diagnostic monitoring system for DPTs (differential pressure transmitters) in nuclear reactor”
o Made use of HART (Highway addressable remote transduction) to access digital information superimposed over the analog
signal of the smart transmitters - Frequency Shift Keying (FSK) principle
o Successfully implemented and tested monitoring system for 16 transmitters, with scope for modular expansion using
additional multiplexers or more channels per multiplexer
National Thermal Power Corporation (NTPC), Delhi, INDIA
Summer Intern (May 1st, 2005– July 31st, 2005)
o Gas and coal based power generation plants
o Analyzed entire process flow to determine efficiency of energy generation, identify wastage hotspots and provide
suggestions for improvement
HONOURS AND AWARDS
o "Delphi Quality Performance Award" for work done at Ford Chicago Assembly Plant
o Selected from a large pool of applicants for Texas government sponsored "Nanoscholar internship", as part of the
Nanoelectronics Workforce Development Initiative
o “Work appreciation award” for overall performance at Sematech
o "First class with distinction" for B.Tech (EIE) degree at Vellore Institute of Technology
LANGUAGES
English, Telugu, Hindi, Tamil, can understand Kannada
AVAILABILITY
Immediate (open to nationwide and international relocation, domestic/international travel acceptable)