Programmable DMA CONTROLLER

1. PROGRAMMABLE DMA CONTROLLER 8237
PREPARED BY
B.SARAVANAMANIKANDAN
ASSISTANTPROFESSOR
Kongunadu college of engineering and technology

2. PIN DIAGRAM
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3. DIRECT MEMORY ACCESS
• The ability of an I/O sub system is to transfer data to and from
memory subsystem which is used for high speed data transfer.
DMA CONTROLLER
• It is a device that can control data transfer between an I/O
subsystem and a memory subsystem without help of the CPU
DMA OPERATIONS
• Once interface is ready to receive data, DMA request is made.
• Bus request is made by the DMA.
• Bus grant is returned by the processor.
• DMA place address on the address bus.
• DMA request is acknowledged.
• Memory places data on the data bus.
• Interfaces latches data.
• Bus request is dropped and control is returned to the processor.
• Bus grant is dropped b the processor
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4. Features of 8237
• Enable / Disable control of individual DMA request.
• Four independent DMA cannels-CH0,CH1,CH2 and CH3.
• Independent auto initialization of all channels
• Memory to memory transfer
• Memory block initialization
• Address increment or decrement
• High speed performance transfer up to 1.6
• Directly expandable to any number of channels
• Software DMA requests
• Independent polarity control for DRQ and DACK signals
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5. BLOCK DIAGRAM
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6. Block diagram of 8257
Data bus buffer:
• It is a 8 bit bidirectional bus with 8 bit buffer which interfaces the
8257 to the system data bus.
• In slave mode it is used to transfer data between microprocessor and
internal registers of 8257
• In master mode it is used to send higher byte address (A8-A15) on
the data bus.
Read/Write Logic:
• When the microprocessor is programming or reading one of the
internal register of 8257, the Read/Write logic accepts the I/O read or
I/O write signal.
• Decodes the LSB(A0-A3) and either writes the contents of the data
bus into the addressed register
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7. • During DMA cycle master mode the Read/Write logic generates the
I/O read and memory write (DMA write machine cycle) or I/O write
and Memory read signal which control the data transfer between
peripheral and memory device.
DMA Channels:
• The DMA provides four identical cannels labeled CH0, CH1,CH2 and
CH3.Each channel has two 16 bit register.
i) DMA address register
ii) Terminal Count Register
DMA address register
It specifies the first memory location to be accessed. It is necessary
to load valid memory address in the DMA address register before
channel is enabled.
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8. Terminal Count Register
• The value loaded into the lower order 14 bits (C10-C0) of TCR
specifies the number of DMA cycles minus (N-1) before TC output is
activated
• For N number of desired DMA cycles it is necessary to load the value
N-1 into the lower order 14 bits of the TCR.
• The MSB 2 bit specifies the type of the operation to be performed.
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9. Control Logic:
• It controls the sequence of operations during all machine cycles by
generating the appropriate control signals and the 16 bit address
specifies the memory location to be accessed.
• It consist of mode set register and Status
• Mode set register is programmed by the CPU to configure 8257 where as
status is read by the CPU to check which channels have reached the
terminal count condition and status update flag.
Mode Set Register:
LSB 4 bits are enable 4 DMA channels
MSB 4 bits are the enable auto load, TC stop, Extended wire, Rotating
priority
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10. STATUS REGISTER:
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11. Priority Resolver:
• It resolves the peripherals request. It can be
programmed to work in two modes either in fixed
mode or rotating priority mode
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12. KNCET EEE DEPARTMENT