calculate the sampling rate for multiple analog signals in a multiplexed system We have a Data acquisition system or DAQ that interfaces 64 inputs through a multiplexer into a single ADC. The ADC needs 0.25 ns to produce a good digital output and during this time its analog input must be stable.   We achieve this using a sample and hold circuit that needs 0.1 ns to Solution The maximum frequency will be 1/(0.35n+0.1n)=2.22GHz. The reason for that is when the signal takes 0.35ns pulse 0.1ns to propogate to the output of sample and hold, the mux can be switched to another input. When the signal takes 0.35ns to propogate to the input of sample and hold block, the ADC has already finished analog to digital convertion which takes 0.25ns. So the sample and hold block can be activated to sample the signal, this will take another 0.1ns. At this time, one cycle is finished, so the frequency should be 1/0.45n=2.22GHz .

1. calculate the sampling rate for multiple analog signals in a multiplexed system
We have a Data acquisition system or DAQ that interfaces 64 inputs through a multiplexer into a
single ADC. The ADC needs 0.25 ns to produce a good digital output and during this time its
analog input must be stable.  We achieve this using a sample and hold circuit that needs 0.1
ns to
Solution
The maximum frequency will be 1/(0.35n+0.1n)=2.22GHz. The reason for that is when the
signal takes 0.35ns pulse 0.1ns to propogate to the output of sample and hold, the mux can be
switched to another input. When the signal takes 0.35ns to propogate to the input of sample and
hold block, the ADC has already finished analog to digital convertion which takes 0.25ns. So the
sample and hold block can be activated to sample the signal, this will take another 0.1ns. At this
time, one cycle is finished, so the frequency should be 1/0.45n=2.22GHz