Understanding Atmega328P Microcontroller Architecture
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Lecture 9 on Understanding Atmega328P
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Understanding Atmega328P Microcontroller Architecture
- 1. Understanding Atmega328P Microcontroller (Lecture-9) R S Ananda Murthy Associate Professor and Head Department of Electrical & Electronics Engineering, Sri Jayachamarajendra College of Engineering, Mysore 570 006 R S Ananda Murthy Understanding Atmega328P Microcontroller
- 2. AVR CPU General Purpose Registers – 32×8 R0 D0D1D2. . . . . . . . . . . .D7 R1 R2 ... R13 R14 R15 0x00 0x01 0x02 0x0D 0x0E 0x0F Addr. R16 R17 ... 0x10 0x11 R26 R27 R28 0x1A 0x1B 0x1C R29 R30 0x1D 0x1E R31 0x1F ...... X Register Low-byte X Register High-byte Y Register Low-byte Y Register High-byte Z Register Low-byte Z Register High-byte Most instructions can access any register and complete operation in one CPU clock cycle. There is also a 16-bit Stack Pointer. Last three register pairs given below can be used as three 16-bit index registers to point at data memory. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 3. X, Y, and Z Registers – 16-bit Pointers to Data D0D1D2. . . . . . . . . .D7 R26 (0x1A)R27 (0x1B) D0D1D2. . . . . . . . . .D7 015 XH XL X-Register D0D1D2. . . . . . . . . .D7 R28 (0x1C)R29 (0x1D) D0D1D2. . . . . . . . . .D7 015 YH YL Y-Register D0D1D2. . . . . . . . . .D7 R30 (0x1E)R31 (0x1F) D0D1D2. . . . . . . . . .D7 015 ZH ZL Z-Register Register pairs R27 and R26, R29 and R28, R31 and R30 known as X, Y, and Z registers – can be used as 16-bit address pointers for indirect addressing of the data space. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 4. Arithmetic Logic Unit (ALU) and Data Path 32 x 8 General Purpose Registers ALU 8 8 Result Status Register H, S, V, N, Z, C Flags Carry Bit Performs arithmetic, logical, or bit-function operations between general purpose registers or between a register and an immediate data within a single CPU clock cycle. Can perform multiplication using on-chip 2-cycle multiplier. Status Register is updated after all ALU operations, as explained in the Instruction Set Reference. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 5. Status Register – for Conditional Branching Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 I – Global Interrupt Enable bit. Explained later. T – Bit Copy Storage. Explained later. H – Half carry flag. Explained later. S – Sign flag. S = N⊕V. Explained later. V – Overflow flag. Explained later. N – The negative flag. N = MSB of result. Z – Zero flag. Z = 1 if result is 0. Z = 0 if result is 1. C – Carry flag. C = 1 if there is carry from D7. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 6. Power On Reset (POR) When Vcc is applied to the AVR microcontroller, it is automatically reset. This is known as Power On Reset (POR). After POR, the Program Counter is loaded with the reset address $0000 so that the instruction present in that location is executed. In Atmega328P, the user has to write a jump instruction (JMP) at location $0000 to jump to the desired application. Other events which can reset the MCU will be explained in detail later. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 7. Clock Distribution in Atmega328P R S Ananda Murthy Understanding Atmega328P Microcontroller
- 8. AVR Clock System Clock Control Unit in side the chip generates clocks for memory and IO devices. Multiple clock signals are generated in side the chip. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. Default is internal 8 MHz R-C oscillator which is divided by 8 by prescaler to give a 1 MHz CPU clock. Default CPU clock is only 5-10% accurate. Option to use external crystal clock source (max 20 MHz) is also available. Selection of system clock by software will be explained later. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 9. Power Management Features in Atmega328P Unused modules can be shut down to save power. Six Sleep Modes – Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby. From power down mode the device can be made to wake up on external reset or when the watchdog timer reset occurs. From power save mode the device can be made to wake up on timer events. Power management by software will be explained later. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 10. Watchdog Timer When MCU is hanging due to any reason, the watchdog timer will timeout and produce an internal reset signal to load the Program Counter with the reset address $0000. During normal operation, the MCU regularly restarts the watchdog timer to prevent it from elapsing, or timing out. More details about watchdog timer will be given later. R S Ananda Murthy Understanding Atmega328P Microcontroller
- 11. License This work is licensed under a Creative Commons Attribution 4.0 International License. R S Ananda Murthy Understanding Atmega328P Microcontroller