Modern+digital+electronics rp+jain

R P Jain
Solution Manual
for
Modern Digital Electronics
Third Edition

CHAPTER 1
1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure
being measured and can assume any value in the given range.
(b) Digital. An electric pulse is produced for every person entering the exhibi-
tion using a photoelectric device. These pulses are counted using a digital
circuit.
(c) Analog. The reading of the thermometer is proportional to the temperature
being measured and can assume any value in the given range.
(d) Digital. Inputs are given with the help of switches, which are converted
into digital signals 1 and 0 corresponding to the switch in the ON or OFF
position. These signals are processed using digital circuits and the results
are displayed using digital display devices.
(e) Analog. It receives modulated signals which are analog in nature. These
signals are processed by analog circuits and the output is again in the
analog form.
(f) Digital. It has only two possible positions (states), ON and OFF.
(g) Digital. An electric pulse is produced for every vote cast by pressing of
switch of a candidate. The pulses thus produced for each candidate are
counted separately and also the total number of votes polled are counted.
1.2 (a)
(i) S1 S2 Bulb (ii) S1 S2 Bulb
OFF OFF OFF OFF OFF OFF
OFF ON OFF OFF ON ON
ON OFF OFF ON OFF ON
ON ON ON ON ON ON
(iii) S Bulb (iv) S1 S2 Bulb
OFF ON OFF OFF OFF
ON OFF OFF ON ON
ON OFF ON
ON ON OFF
(b)
(i) S1 S2 Bulb (ii) S1 S2 Bulb
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
(iii) S Bulb (iv) S1 S2 Bulb
0 1 0 0 0
1 0 0 1 1
1 0 1
1 1 0
(c) (i) AND (ii) OR (iii) NOT (iv) EX-OR

2
1.3
1.4
Inputs Outputs of
A B (a) (b) (c) (d)
0 0 1 1 0 0
0 1 0 1 0 1
1 0 0 1 0 1
1 1 0 0 1 1
The operations performed are
(a) NOR (b) NAND (c) AND (d) OR
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0 1 2 3 4 5 t(ms)
0 1 2 3 4 5 t(ms)
Input B
AND
OR
NAND
NOR
EX-OR
Input A

3
1.5 For Fig. 1.6
(a) A Y (b) A B AB Y
0 1 0 0 1 0
1 0 0 1 1 0
1 0 1 0
1 1 0 1
(c) A B A B Y
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 1
For Fig. 1.8
(a) A Y (b) A B A B+ Y
0 1 0 0 1 0
1 0 0 1 0 1
1 0 0 1
1 1 0 1
(c) A B A B Y
0 0 1 1 0
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
1.6 (a) NAND, NOR (b) AND
(c) NAND (d) OR
1.7 (a)
Inputs AB A B Output
A B Y
0 0 0 0 0
0 1 0 1 1
1 0 1 0 1
1 1 0 0 0
(b) EX–OR
(c) A
B
Y

4
(d) Y = AB A B+
Y = +AB A B
= ⋅AB AB
Y = Y = ⋅AB AB
= ⋅Y Y1 2
where, Y1 = AB and Y2 = AB
A
B
Y
Y1
Y2
1.8 For simplicity, we shall consider 2-input gates, but the results are equally
valid for any number of inputs. In the positive logic system, the higher of the
two voltages is designated as 1 and the lower voltage as 0. On the other hand
in the negative logic system, the lower of the two voltage is designated as 1
and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic
system will change from positive to negative and vice-versa.
(a) In the truth table of positive logic AND gate replace all zeros by ones
and all ones by zeros. The resulting truth table is same as that of the OR
gate. Similarly, if all ones and zeros are interchanged in the truth table
of the OR gate, the resulting truth table will be same as that of the AND
gate.
(b) Repeat part (a) for NAND and NOR gates.
1.9 (a) A + AB + AB = (A + AB ) + AB
= A (1 + B ) + AB
= A × 1 + AB
= A + AB
= (A + A ) (A + B) = A + B
(b) AB + A B + A B = (A + A) B + A B
= B + A B = (B + A) (B + B )
= A + B
(c) ABC + AB C + ABC + ABC
= ABC + AB C + AB (C + C )
= ABC + AB C + AB
= ABC + A (B + B C)
= ABC + A (B + B ) (B + C)

5
= ABC + AB + AC
= C (A + AB) + AB
= C (A + A) (A + B) + AB
= C (A + B) + AB
= AB + BC + CA
1.10 (a)
A B A B AB A + A B + AB A + B
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 1 1
(b)
A B AB A B A B AB + A B + A B A + B
0 0 0 0 1 1 1
0 1 0 1 0 1 1
1 0 0 0 0 0 0
1 1 1 0 0 1 1
(c)
A B C A BC AB C ABC ABC LHS AB BC CA RHS
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 1 0 1 0 1
1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 0 1 0 0 1 1
1 1 0 0 0 1 0 1 1 0 0 1
1 1 1 0 0 0 1 1 1 1 1 1
1.11 (a) The realization of LHS requires, two inverters, two 2-input AND gates,
and one 3-input OR gate, whereas the realization of RHS requires only
one two input OR gate.
A
B
A
B
(ii)(i)

6
(b) The realization of LHS requires two inverters, three 2-input AND gates
one inverter and one 2-input OR gate.
A
B
A
B
(c) The realization of LHS requires three inverters, four 3-input AND gates
three 2-input AND gates and one 3-input OR gate.
A
B
C
(i)
A
B
C
(ii)
1.12 (a) AB + CD = + = ⋅AB CD AB CD
(i) (ii)

7
(b) (A + B) (C + D) = + ⋅ +( ) ( )A B C D
= + + +( ) ( )A B C D
(i) The left hand side of (a) can be realized by using two 2-input AND
gates followed by one 2-input OR gate, while the right hand side is
realizable by two 2-input NAND gates followed by another 2-input
NAND gate. Hence an AND-OR configuration is equivalent to a NAND-
NAND configuration.
(ii) The left hand side of (b) is realizable by two 2-input OR gates followed
by a 2-input AND gate, while the right hand side is realizable by two
2-input NOR gates followed by another 2-input NOR gate. Hence an
OR-AND configuration is equivalent to a NOR-NOR configuration.
1.13
Y
A
B
C
D
Y
A
B
C
D
(i) (ii)
A
B
C
D
A
B
C
D
(i) (ii)
Y Y
1.14 (a) Since A × B = B × A
Therefore, the AND operation is commutative. If A × (B × C) = (A × B) × C, then the
AND operation is associative. This can be proved by making truth table as given
below:
A B C (A × B) × C A × (B × C)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
(a)
(b)

8
Since the last two columns of the truth table are identical, which proves
that the AND operation is associative.
(b) Since, A + B = B + A, therefore, OR operation is commutative.
The associative property requires
A + (B + C) = (A + B) + C
which can be proved by making the truth table in a way similar to the
truthtable of (a) above
(c) Since, A Å B = B Å A, which means the EX-OR operation is commutative.
The associative property requires
(A Å B) Å C = A Å (B Å C)
This can be proved by making truth table
1.15 (a) Since = ⋅ = ⋅A B B A, therefore, the NAND operation is commutative.
To verify whether the NAND operation is associative or not, we prepare
the truth table as given below. From the Table we observe that the last
two columns are not identical, which means
A B C A B C⋅ ⋅ ≠ ⋅ ⋅( ) ( )
This shows that the NAND operation is not associative.
A B C A B C⋅ ⋅( ) ( )A B C⋅
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1
(b) Since, A B B A+ = + , which means the NOR operation is commutative.
By making a truth table similar to the truth table of (a) above we can
verify that
( ) ( )A B C A B C+ + ≠ + +
Therefore, the NOR operation is not associative.
1.16 Two possible realizations are given on page 9:
1.17 (i) If only one of the variables is 1 and all others are zero, then
(1 Å 0) Å 0 Å 0 Å . . . = 1 Å 0 Å 0 Å . . .
= 1 Å 0 = 1
(ii) If only two of the variables are 1 and all others are zero, then (since EX-
OR operation is commutative and associative)
(1 Å 1) Å 0 Å 0 Å 0 Å . . . = 0 Å 0 Å 0 Å 0 Å . . . = 0
(iii) Similarly, if only three of the variables are 1, then
(1 Å 1) Å 1 Å 0 Å 0 Å . . .
= 0 Å 1 Å 0 Å 0 Å 0 Å . . .
= 1

9
A
B
C
D
A Å B
AÅ B ÅC
A Å B Å C Å D
Y
or
A
B
C
D
A Å B
C Å D
Y
A Å B Å C Å D
Fig. 1.17
In the same way we can try higher number of ones. It is obvious from
the above discussion that Z = 1, if an odd number of variables are 1 and
Z = 0 if an even number of variables are 1.
1.18 Since a logical variable can assume one of the two values (0 or 1) the
number of possible combinations is 2N
.
Take an N-bit binary number bN–1 bN–2 . . . b2b1b0 and write all combina-
tions from 00 . . . 000 to 11 . . . 111 in normal binary ascending order.
1.19 (a) 7402 is a quad 2-input NOR gate. This means there are four identical
2-input NOR gates. Each gate requires three pins, two for inputs and one
for output. Therefore, the four gates requires 3 ´ 4 = 12 pins. Two pins
are required for the power supply (VCC and GND). Hence it is a 14-pin
IC.
(b) 7404 is a hex inverter.
The number of pins = 2 ´ 6 + 2 = 14.
(c) 7408 is a quad 2-input AND gate.
(d) 7410 is a triple 3-input NAND gate.
(e) 7411 is a triple 3-input AND gate.
(f) 7420 is a dual 4-input NAND gate.
Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC.
Two pins are left free (NC).
(g) 7427 is a triple 3-input NOR gate.
(h) 7432 is a quad 2-input OR gate.

10
(i) 7486 is a quad EX-OR gate.
1.20 (a) (i) 7408 and 7432
(ii) 7400
(b) (i) 7432 and 7408
(ii) 7402
1.21 Logic Circuit A
0.4V = 0
2V = 1
Logic Circuit B
–0.75V = 1
–1.55V = 0
1.22
Inputs Output
AND OR NAND NOR
A B C Y1 Y2 Y3 Y4
0 0 0 0 0 1 1
0 0 1 0 1 1 0
0 1 0 0 1 1 0
0 1 1 0 1 1 0
1 0 0 0 1 1 0
1 0 1 0 1 1 0
1 1 0 0 1 1 0
1 1 1 1 1 0 0
1.23 Yes.
A
B
C
Logic 1
or YY
A
B
C
(a)
Y
A
B
C
or
A
B
C
Y
Logic 0
(b)
A
B
C
A
B
C
orY Y
Logic 1
(c)
A
B
C
A
B
C
orY Y
Logic 0
(d)

11
1.24 Yes.
AND — by connecting one of the inputs to logic 0
OR — by connecting one of the inputs to logic 1
NAND — by connecting one of the inputs to logic 0
NOR — by connecting one of the inputs to logic 1.
1.25 (a) Active-high (b) Active-low
(c) Active-high (d) Active-low
1.26 (a) Active-low (b) Active-high
(c) Active-low (d) Active-high
1.27 (a)
(b)
A
B
C
Y
A
B
C
Y = A + B + C = (A + B) + (C)
(c)
A
B
C
Y
AB
C
Y = A × B × C = (A × B) × (C)
Y A B C= ⋅ ⋅ = ⋅ +( )A B C
= ⋅ ⋅( )A B C
= ⋅ ⋅A B C
(d)
A
B
C
Y
AB
Y

12
1.28 (a) A Å B = AB + A B
A Å B = AB AB+
= AB + AB = A Å B
(b) A B⊕ = AB + AB
A Å B = AB A B+
= AB + AB
A Å B = AB AB AB AB+ = +
(c) B Å (B Å AC) = B Å B Å AC = 0 Å AC
= AC

13
CHAPTER 2
2.1
(a) 111001 = 1 ´ 25
+ 1 ´ 24
+ 1 ´ 23
+ 0 ´ 22
+ 0 ´ 21
+ 1 ´ 20
= 32 + 16 + 8 + 0 + 0 + 1
= (57)10
(b) 101001 = 1 ´ 25
+ 0 ´ 24
+ 1 ´ 23
+ 0 ´ 22
+ 0 ´ 21
+ 1 ´ 20
= 32 + 0 + 8 + 0 + 0 + 1
= (41)10
(c) 11111110 = 1 ´ 27
+ 1 ´ 26
+ 1 ´ 25
+ 1 ´ 24
+ 1 ´ 23
+ 1 ´ 22
+ 1 ´ 21
+ 0 ´ 20
= 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10
(d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10
(e) 1101.0011 = 1 ´ 23
+ 1 ´ 22
+ 0 ´ 21
+ 1 ´ 20
+ 0 ´ 2–1
+ 0 ´ 2–2
+ 1 ´ 2–3
+ 1 ´ 2–4
= 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0.0625
= (13.1875)10
(f) 1010.1010 = 8 + 2 + 0.5 + 0.125
= (10.625)10
(g) 0.11100 = 0.5 + 0.25 + 0.125
= (0.875)10
2.2 (a) Quotient Remainder
37
2
18 1
18
2
9 0
9
2
4 1
4
2
2 0
2
2
1 0
1
2
0 1
1 0 0 1 0 1
Thus (37)10 = (100101)2
Similarly,
(b) (255)10 = (11111111)2
(c) (15)10 = (1111)2

14
(d) Integer part: (26)10 = (11010)2
Fractional part:
0.25 0.5
´ 2 ´ 2
0.5 1.0
¯ ¯
0 1
Therefore, (26.25)10 = (11010.01)2
(e) Integer part: (11)10 = (1011)2
Fractional part: 0.75 0.5
´ 2 ´ 2
1.5 1.0
¯ ¯
1 1
Thus (11.75)10 = (1011.11)2
(f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8
´ 2 ´ 2 ´ 2 ´ 2 ´ 2 ´ 2 ´ 2 ´ 2
0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6
¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯
0 0 0 1 1 0 0 1...
Thus, (0.1)2 = (0.00011001)2
The process may be terminated at the required number of significant bits.
2.3 (a) 1 1 1 ¬ Carry
1 0 1 1
+1 1 0 1
1 1 0 0 0

Final carry
(b) 1 1 1 1 1 ¬ Carry
1 0 1 0. 1 1 0 1
+ 1 0 1. 0 1
1 0 0 0 0. 0 0 0 1

Final carry
2.4
(a) 01000 01000
–01001 + 10111 (2’s complement)
11111
Since the MSB of the sum is 1, which means the result is negative and it is
in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10
Therefore, the result is –1.

15
(b) 01100 Þ 01100
–00011 + 11101 (2’s complement)
101001 = + 9

Ignore
(c) 0011.1001 Þ 0011.1001
–0001.1110 +1110.0010 (2’s complement)
10001.1011 = + 1.6875

Ignore
375
8
46 7
46
8
5 6
5
8
0 5
5 6 7
Therefore, (375)10 = (567)8 = (101110111)2
(b) Quotient Remainder
249
8
31 1
31
8
3 7
3
8
0 3
3 7 1
Therefore, (249)10 = (371)8 = (011111001)2
(c) Integer part: (27)10 = (33)8 = (011011)2
Fractional part: 0.125
´ 8
1.000
¯
1
Thus (0.125)10 = (0.1)8 = (0.001)2
Therefore, (27.125)10 = (33.1)8 = (011011.001)2
2.6 (a) 11 011 100.101 010 = (334.52)8
(334.52)8 = 3 ´ 82
+ 3 ´ 81
+ 4 ´ 80
+ 5 ´ 8–1
+ 2 ´ 8–2
= (220.65625)10
(b) 01 010 011.010 101 = (123.25)8 = (83.328125)10
(c) 10 110 011 = (263)8 = (179)10

16
375
16
23 7
23
16
1 7
1
16
0 1
1 7 7
Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2
(b) Quotient Remainder
249
16
15 9
15
16
0 15
F 9
Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001)2
(c) Integer part:
Quotient Remainder
27
16
1 11
1
16
0 1
1 B
Thus (27)10 = 1BH
Fractional part:
0.125
´ 16
2.000
¯
2
(0.125)10 = 0.2H
(27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2
2.8 (a) 1101 1100.1010 10 = (DC.A8)16
(DC.A8)16 = 13 ´ 161
+ 11 ´ 160
+ 10 ´ 16–1
+ 8 ´ 16–2
= (220.65625)10
(b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10
(c) 1011 0011 = (B3)16 = (179)10
2.9 For each decimal digit write its natural BCD code
(a) 46 = 0100 0110 (BCD)
(b) 327.89 = 0011 0010 0111.1000 1001 (BCD)
(c) 20.305 = 00100000.0011 0000 0101 (BCD)
2.10 For each decimal digit write its 4-bit Excess-3 code.
(a) 46 = 0111 1001 (Excess-3)
(b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3)
(c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3)

17
2.11 Starting from 4-bit Gray code given in Table 2.8 formulate 5-bit Gray code as
given below in Table 1.
Table 1 Table 2
Decimal G4 G3 G2 G1 G0 Decimal G5 G4 G3 G2 G1 G0
No. No.
0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 1 0 0 0 0 0 1
2 0 0 0 1 1 2 0 0 0 0 1 1
: : : 3 0 0
: : : : 0
13 0 1 0 1 1 17 0 1 1 0 0 1
14 0 1 0 0 1 : 0
15 0 1 0 0 0 30 0 1 0 0 0 1
16 1 1 0 0 0 31 0 1 0 0 0 0
17 1 1 0 0 1 32 1 1 0 0 0 0
18 1 1 0 1 1 33 1 1 0 0 0 1
: : : 1
: : 46 1 1 1 0 0 1
29 1 0 0 1 1 : 1
30 1 0 0 0 1 62 1 0 0 0 0 1
31 1 0 0 0 0 63 1 0 0 0 0 0
Similarly, form 6-bit Gray Code as given in Table 2.
From Table 2, we obtain
(46)10 = 111001 (Gray Code)
2.12 Writing the 6-bit code for each character (See Table 2.9), we obtain
100111 001011 000011 101100 101000
2.13 (a) Write the 7-bit ASCII code for each character (See Table 2.10)
R.P. JAIN = 1010010 0101110 1010000 0101110 1001010
1000001 1001001 1001110
(b) Write the 8-bit EBCDIC code for each character (See Table 2.9)
R.P. JAIN = 11011001 01001011 11010111 01001011 11010001
11000001 11001001 11010101
(c) Write the 6-bit internal code for each character (See Table 2.9)
R.P. JAIN = 101001 011011 100111 011011 100001 010001
011001 100101
2.14 (a) Count the number of ones for every character from ASCII table and
attach a 1 or 0 as the MSB for odd or even number of ones respectively.
For example, the ASCII code for R is 1010010, which has three ones.
Therefore, a 1 is to be attached as MSB and the resulting 8-bit code
with even parity will be
11010010
Similarly, the code for l is 0101110 which has four ones. Therefore, a
0 is to be attached as MSB and the resulting 8-bit code with even parity
will be 00101110.

18
In a similar way parity bit can be attached to every character.
(b) Repeat part (a) for EBCDIC code.
2.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. For example,
8-bit ASCII code for R with odd parity is 01010010
(b) Repeat part (a) for EBCDIC code.
2.16 (a) Since, 25
= 32 and 26
= 64, therefore, the minimum number of bits
required to encode 56 elements of information is 6.
(b) 27
< 130 < 28
Therefore, 8 bits are required to encode 130 elements of information.
2.17 In the 8 bit ASCII code with the parity bit, if binary to hexadecimal conversion
is used, the resulting format will be hexadecimal. For example,
R = 11010010 = D2 H
and l = 00101110 = 2EH
for even parity and
R = 01010010 = 52H
and l = 10101110 = AEH
for odd parity.
2.18 Consider the following examples:
(i) 7 0111 Þ 0111
–3 –0011 + 1100 (1’s complement)
4 10011
1 End-Around Carry (EAC)
0100 = 4
(ii) 3 0011 Þ 0011
–7 – 0111 + 1000 (1’s complement)
–4 1011 = –4 in 1’s complement form
From the above examples the rules of subtraction can be summarized as:
(a) Add ones complement of the subtrahend to the minuend.
(b) If a carry is produced, add end-around carry (EAC)
(c) If the MSB of the sum is 0, the result is positive
(d) If the MSB of the sum is 1, the result is negative and it is in one’s
complement format.
2.19 100 ´ 20 ´ 8 bits.
2.20 132 ´ 7 bits.
2.21 Let us consider the BCD code for 9 and find out its Hamming code for
error correction.
Hamming Code
Decimal Position ® 1 2 3 4 5 6 7
digit p1 p2 n1 p3 n2 n3 n4
9 BCD : : 1 : 0 0 1
: : : : : : :
odd parity for : : : : : : :
1,3,5,7 requires p1 = 1 1 : 1 : 0 0 1
odd parity for 2,3,6,7 : : : : : : :
requires p2 = 1 1 1 1 : 0 0 1
odd parity for 4,5,6,7 : : : : : : :
requires p3 = 1 1 1 1 0 0 0 1

19
Therefore, Hamming code for decimal digit 9 is 1 1 1 0 0 0 1.
Similarly, Hamming code is determined for each BCD digit and the complete se-
quence is given below.
Hamming code
Decimal Position ® 1 2 3 4 5 6 7
digit p1 p2 n1 p3 n2 n3 n4
0 1 1 0 1 0 0 0
1 0 0 0 0 0 0 1
2 1 0 0 0 0 1 0
3 0 1 0 1 0 1 1
4 0 1 0 0 1 0 0
5 1 0 0 1 1 0 1
6 0 0 0 1 1 1 0
7 1 1 0 0 1 1 1
8 0 0 1 1 0 0 0
9 1 1 1 0 0 0 1

20
CHAPTER 3
3.1 (a) The number of covalent bonds breaking away increases with temperature,
which decreases the resistivity of the semiconductor material, whereas in a
metal an increase in the temperature results in a greater thermal motion of
the ions, and hence decreases the mean free path of the free electrons. This
results in a decrease in the mobility and hence resistivity increases with
temperature.
(b) All the covalent bonds are intact at 0 K and hence there are no free charge
carriers, whereas at room temperature some of the covalent bonds break
away resulting in small conductivity.
3.2 (a) Using the V-I relation of the diode, we obtain
I1 » I0 exp (V1/hVT) (3.1)
and I2 = 2I1 » I0 exp (V2/hVT) (3.2)
From Eqs. (3.1) and (3.2),
2 = exp (V2 – V1/hVT)
or V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0.693 mV » 36 mV
(b) Since, V1 = 700 mV
Therefore, V2 = 700 + 36 = 736 mV
Percentage change =
−
×
736 700
700
100%
= 5.14%
3.3 From the V–I relation of the diode, we obtain
I1 » I0 exp (700/hVT)
and I2 » I0 exp (750/hVT)
I2/I1 = exp (50/2 ´ 26) = 2.616
or I2 = 2.616 ´ 2 = 5.232 mA
(b) Percent change =
−
×
5 232 2
2
100
.
%
= 161.6%
3.4
I
I
2
1
= 10 = e {(V2 – V1)/2 ´ 26}
or V2 – V1 = 52 1n 10 = 119.73 mV
3.5 (a) The circuit will be under steady-state at t = 20ms,
i.e.,
dQ
dt
= 0

21
∴ ≈I
V
R1
1
= =
10
10
1mA
Since,
Q
t
= I
Q = 1 ´ 10–6
´ 10–3
= 10–9
C
(b) The diode will turn off when excess minority charge has been removed.
I
V
RR
R
≈ = =5
10
0 5. mA
The differential equation is
dQ
dt
Q
+ = − × −
τ
0 5 10 3.
Solving this with initial condition
Q(0) = 10–9
C (part (a)), we obtain
Q = – 0.5 ´ 10–9
+ 1.5 ´ 10–9
e–t
Set Q = 0 for cut-off
t = 1.099 ms
(c) The various waveforms are given below. The recovery time constant
tR = RCO = 10 ´ 103
´ 10 ´ 10–12
= 0.1 ms
Vi
V1 = 0V
0
-V2 = -5V
Vd
0.7V
0
-5V
Id
1 mA
0
-0.5 mA
Q
0
Excess
Minority
Charge
0 1.099 ms
t
t
t
t
tR
tR
t

22
3.6 (a) Since the E-B junction is forward-biased, therefore, the transistor is con-
ducting (i.e., IC is flowing). It may either be operating in the active region
or in the saturation region.
Let us assume that the transistor is operating in the saturation region.
Then the base and collector voltages will be VBE, sat (= 0.8 V) and VCE, sat
(= 0.1 V) respectively.
Therefore, the collector current IC and the base current IB are given by
IC
=
−
=
−
=
V V
R
CC CE
C
, .
.
sat
mA
10 0 1
3
3 33
and IB =
−
=
−
=
V V
R
BB BE
B
, .sat
A
5 0 8
200
21 µ
hFE ⋅IB = 21 ´ 100 = 2.1 mA
Since IC>hFE IB, therefore the transistor cannot be in saturation. Hence it is
conducting in the active region.
with VCC = 6V, let us again assume that the transistor is operating in the
saturation region. Therefore,
IC =
−
≈
6 0 1
3
2
.
mA
The current IB remains same as in part (a).
Therefore, now
IC < hFEIB
which means the transistor is certainly operating in the saturation region.
(b) The value of RC required for the transistor to be in saturation is given by
V V
R
h I
CC CE
C
FE B
−
≤
,sat
or RC ≥
−10 0 1
2 1
.
.
kW
³ 4.7 kW
The value of Rc just sufficient for saturation will be 4.7 kW.
If the value of RC used is more than 4.7kW, the transistor will continue to
be operating in the saturation region.
(c) The value of RB required to drive the transistor into saturation is given by
IC ≤ ×
−
h
V V
RFE
BB BE
B
,sat
or RB ≤ ⋅
−
100
5 0 8
3 3
.
.
kW
£ 127.27 kW

23
The value of RB just sufficient to drive the transistor into saturation will be
127.27 kW. If a smaller value of RB than the value calculated above is
used, the transistor will be driven deeper into saturation.
3.7 (a) For the transistor to be in the cut-off region, the voltage
VBB £VBE, cut–in
£ 0.5 V
(b) For active region operation
V V
R
V V
R
h
CE CE
C
BB BE
B
FE
−
≥
−
⋅
, ,sat sat
or, VBB < ⋅
−
+
R
R
V V
h
VB
C
CC CE
FE
BE
,
,
sat
sat
< ⋅
−
+
100
2
5 0 1
100
0 8
.
.
< 3.25 V
Therefore, the range of VBB for active region is
0.5 V < VBB < 3.25 V
(c) The range of VBB for saturation region is
VBB ³ 3.25 V
3.8 For the transistor to be in saturation
V V
R
CC CE
C
− ,sat
≤
−
⋅
V V
R
h
BB BE
B
FE
,sat
or, hFE (min) = ⋅
−
−
R
R
V V
V V
B
C
CC CE
BB BE
,
,
sat
sat
= ⋅
−
−
200
1
5 0 1
5 0 8
.
.
= 233.3
3.9 Assume the transistor to be in saturation. Writing KVL equations for the
collector and base circuits,
RCIC + VCE, sat + RE (IC + IB) = VCC
and RBIB + VBE, sat + RE (IC + IB) = VBB
Substituting the values, we obtain,
53 IC + 50 IB = 4.8

24
and 50 IC + 100 IB = 4.2
Solving these equations,
IC = 0.096 mA
and IB = –6.214 mA
Since IB comes out to be negative, hence the transistor is not in saturation.
Assuming VBE = 0.7 V in the active region, KVL for the base circuit
will be
[RB + (1 + hFE) RE] IB = 5 – 0.7
or, IB = 8.43 ´ 10–4
mA
IC = hFE IB = 8.43 ´ 10–2
mA
and IE » –8.43 ´ 10–2
mA
3.10 The equivalent circuit at the input of a transistor consists of input resistance Ri
in parallel with the input capacitance Ci as shown in Fig. given below:
When fast changes occur in Vi, the voltages at B change with the time con-
stant
Ci (RB||Ri)
If a capacitor C is connected across RB, the voltage at B will change as soon as
Vi changes because of the capacitive voltage divider. This helps in improving
the switching speed of transistor circuit.
3.11 (a) For the load transistors
IC,sat = =
5V
2 k
2.5 mA
W
IB,sat = =
2 5
2 5
.
.
mA
100
Aµ
The minimum value of Vi required for the load transistors to be in satura-
tion is
Vi(min) = 25 ´ 10–3
´ 10 + 0.8
= 1.05 V
C
Ri
RB
B
Ci
Vi
+
–
Equivalent circuit at the
transistor input

25
(b) Assuming the load transistors to be in saturation the equivalent circuit at
their input will be as shown in Fig. (a), which reduces to the circuit shown
in Fig. (b).
Now, the voltage Vi = VO can be determined using the principle of super-
position and is given by
Vi
5 2
5 0.8
5 2 5 2
= = ´ + ´
+ +
OV
= 3.8 V
10 kW
0.8 V
10 kW
5 kW
0.8 V
0.8 V
Vi
Vi
(a) (b)
(c) The base current IB1 = =
−
I B2
3 8 0 8
10
. .
mA
= 0.3 mA
3.12(a) When both the transistors are cut-off, there is no current drawn from the
supplies, and the voltage at Y is 5 V.
(b) When both the transistors are in saturation, the voltage at Y is 0V.
(c) Assume T1 to be cut-off and T2 to be in saturation. Since T2 is in saturation,
the voltage at Y will be 0 V. The currents I1 and I2 will be same
æ ö
=ç ÷è ø
CC
C
V
R
and IC2 = I1 + I2.
Similarly, if T1 is in saturation and T2 is cut-off then IC1 = I1 + I2
(d) V1 V2 Y
0V 0V 5V
0V 5V 0V
5V 0V 0V
5V 5V 0V
It performs NOR operation.
3.13 (a) Assume the transistor to be in saturation.
Therefore, IC = = =
−
=
5
1
5
5 0 8
100
0 042mA mA,
.
.IB
hFE IB = 150 ´ 0.042 = 6.3 mA
Since IC < hFE IB, therefore, the transistor is definitely in saturation.

26
(b) When S1 is closed, I1 = (5 – 0.7/4) = 1.075 mA assuming the transistor to
be in saturation.
Therefore, IC = I + I1
= 5 + 1.075
= 6.075 mA
Since IC < hFE ⋅ IB
Therefore, the transistor continues to remain in saturation.
(c) When both S1 and S2 are closed, if we again assume the transistor to be in
saturation,
IC = I + I1 + I2
= 5 + 2 ´ 1.075
= 7.15
Now IC <hFE⋅IB
Which means the transistor no longer remains in saturation. Therefore, it
is conducting in the active region.
3.14 The base current required for each transistor to be in saturation is 25mA.
Therefore, total base current will be 25 ´ 100 mA. If this current flows
through RC of driver, the voltage at its collector will be
VO = 5 – 2 ´ 103
´ 25 ´ 100 ´ 10–6
= 0
Which shows that it is not possible to have a base current of 25 mA for each
of the load transistor. Hence, the load transistors will not remain in saturation.
3.15 Let T1 be cut-off. Therefore, the circuit will be as shown below:
VCC
RC
VCC
RC
T2
T1
Now, the total resistance in the collector circuit of T2 is RC || RC = RC/2 which
means its collector current increases. This requires the base current to be
doubled for the transistor to remain in saturation. Therefore, the transistor will
be operating in the active region.
3.16 The effective resistance = RC || RC =
RC
2

27
Therefore, the time constant = ⋅
R
C
C
O
2
3.17 (a) Since VGS = 0, therefore, the VDS VS ID characteristic will be same as the
characteristic for VGS = 0 in Fig. 3.41(b).
(b) Transistor T2 acts as load for T1, the v-i characteristic of the load is that of
part (a). Since the current ID is same in both T1 and T2, therefore, for a
given value of ID, the voltage.
VDS1 = VDD – VDS2
Take various values of ID and for each ID determine VDS2 from the
curve of (a).
Calculate VDS1 and locate a point corresponding to VDS1, ID on the char-
acteristic of Fig. 3.28. Thus, we get a load curve AB as shown below.
From this we see that when
Vi = 0, VO = 5V
and Vi = 5V, VO » 0V
Therefore, the circuit functions as an inverter.
B
0 5 10 VDS, V
ID, mA
4
3
2
1
0
VGS = 5 V
4 V
3 V
2 V
1 V
Load curve
A

28
CHAPTER 4
4.1 When the output of the driver gate is high, the load gates are in saturation and
T1 and T2 are cut-off. Therefore, VO = 1.14V. The current drawn from the
supply,
I
V V
R
CC O
C
1
3 6 1 14
640
3 844=
−
=
−
=
. .
. mA
when the output of the driver is low, T1 and/or T2 are in saturation and
VO = 0.2V.
The current drawn from the supply
I2 =
−
=
3 6 0 2
640
5 312
. .
. mA
Average current = =
+
=
+
I
I I
av
1 2
2
3 844 5 312
2
. .
= 4.578 mA
Average Power drawn from the supply = VCC ´ Iav
= 3.6 ´ 4.578 mW
= 16.48 mW
4.2 (a) & (b)
hFE = 10 hFE = 20
N VO Noise Margin VO Noise Margin
D1 D1
5 1.14 0.1 1.14 0.22
6 1.09 0.05 1.09 0.17
7 1.055 0.015 1.055 0.135
8 <1.04 Load gate transistors
not in saturation 1.026 0.106
9 <1.04 ’’ 0.997 0.077
10 <1.04 ’’ 0.984 0.064
The voltage VO and noise margin D1 are given in Table.
(c) Fan out and noise margin increases with increase in hFE.
(d) For hFE = 10, if N > 7, the load gate transistors come out of saturation.
The value of noise margin decreases with increased N.
4.3 (a) Let us consider all the possible cases:
Case I A = B = C = D = 0.
Therefore, all the transistors TA, TB, TC, and TD are cut-off, hence
Y = Y1 = Y2 = 1
Corresponding to this, each gate will be able to drive 5 gates. Therefore,
the fan-out of this combination will be 10. Alternatively, we can consider

29
equivalent collector resistance R¢C = RC || RC = RC/2, which means the base
current of 5 + 5 load transistors can flow through R¢C and give same output
voltage corresponding to logic 1 as the output voltage of each gate individ-
ually while driving 5 load gates.
Case II At least one of the inputs of each gate P and Q are HIGH. This
will drive the corresponding transistors into saturation and consequently
Y = Y1 = Y2 will be LOW and hence the load transistors will be cut-off.
Therefore, there is no problem of fan-out.
Case III At least one of the inputs to gate P is HIGH and C = D = 0. The
transistor whose input is HIGH will be driven to saturation forcing the
output voltage to LOW. Consequently, Y = Y1 = Y2 will be LOW and this
situation is similar to that of Case II.
Case IV A = B = 0 and at least one of the inputs to gate Q is LOW. This
will lead to a situation similar to that of Case III.
Therefore, the fan-out is 10.
(b) Without load gates, the propagation delay time-constant
= ⋅
R
C
C
O
2
2
= RC ⋅ CO
which is same as the propagation delay time-constant of a single gate.
With load gates, the propagation delay time-constant for a single driver
(without wired-logic) is
( )
æ ö
+ × +ç ÷è ø
B
C O i
R
R C NC
N
where, N is the number of load gates.
RB is the resistance in the base circuit of a load gate.
Ci is the input capacitance of a load gate. With wire-ANDing, the time-
constant will be
( )2
2
æ ö
+ × +ç ÷è ø
C B
O i
R R
C NC
N
When the output is high, the current drawn from the supply is
IH = 3.844 ´ 2 mA (see Prob. 4.1)
Similarly, for low output
IL = 5.312 ´ 2 mA
Iav = 9.156 mA
Power drawn from the supply = 3.6 ´ 9.156 mW
= 32.96 mW
4.4 (a) This circuit has active pull-up (consisting of T2 and 100 W resistor) instead
of passive pull-up RC used in normal RTL gates. The state of transistor T2

30
will always be opposite to that of T3, i.e., if T3 is cut-off, T2 is in saturation
(since T1 is cut-off) and vice-versa. Therefore, when the input Vi is HIGH,
T3 will be in saturation, while T2 is cut-off and VO = VCE,sat » 0 V.
When Vi is LOW, T2 is in saturation and T3 is cut-off. The output
voltage VO will be HIGH.
(b) If it is driving N load gates, the output circuit corresponding to HIGH state
will be as shown in Fig. Prob. 4.4(a).
640 W
450 W
100 W
VCC(3.6 V)
T2
IB IO
450 W/N
VBE, sat
» 0.8 V
P
Equivalent
input circuit
of load gates
Fig. Prob. 4.4(a)
IO =
− −
+
V V V
N
CC CE BE, ,
/
sat sat
100 450
=
− −
+
3 6 0 2 0 8
100 450
. . .
/ N
=
+
2 6
100 450
.
/ N
Writing KVL for the closed path P, we obtain
VCC – 1090 IB – VBE, sat −
450
N
IO – VBE, sat = 0
or IB
450 2.61
3.6 0.8 0.8
1090 100 450/
é ùæ ö
= - - -ê úç ÷+è øê úë ûN N
For T2 to be in saturation
hFE.IB ³ IO

30 450 2.6 2.6
2
1090 100 450/ 100 450/
é ùæ ö
- ´ ³ê úç ÷+ +è øê úë ûN N N
From the above equation, we obtain N ³ 2.5. Therefore, N ³ 3 since N is an
integer.

31
Since, I1 = I2 = . . . = IN.
Therefore, IO =
+
= ⋅
2 6
100 450 1
.
/ N
N I
The values of I1 for various values of N are given in Table
Table
N1 I1 (mA)
30 750
40 585
50 480
60 403
70 349
The base current required for saturation for a normal RTL is about 300 mA,
which means N can be taken as 70, which is very large.
(c) The relevant portion of the circuit is shown in Fig. Prob. 4.4(b). Here T3A
and T2B are in saturation, whereas T2A and T3B are cut-off. Neglecting the
base currents
IE2B = =
− −
IC A3
3 6 0 2 0 2
100
. . .
= 32 mA
VCC = 3.6 V
100 W 100 W
T2A
T2B
IC3A
T3A T3B
A = 1 B = 0
Fig. Prob. 4.4(b)
4.5 (a) When all the inputs are HIGH the voltage at the point P will be Vp = 0.8 +
0.7 = 1.5 volts.
∴ =
−
=I1
5 1 5
5
0 7
.
. mA
and IB = 0.7 – 0.16 = 0.54 mA
This will increase the fan-out to 17, but the noise margin D0 will be
reduced from 0.8 V to 0.2 V.
IE2B

32
(b) In this case VP = 0.8 + 0.7 ´ 3 = 2.9 V
I1 = 0.42 mA, and IB = 0.26 mA
This will reduce the fan-out to 6, but the noise margin D0 will be increased
to 1.4 V.
4.6 For a fan-out of 10,
0.82 ´ 10 + 2.182 = hFE ´ 0.4
or hFE » 26
4.7 The Fig. Prob. 4.7 shows the relevant portion of the circuit. The worst condi-
tion corresponds to the situation when the output transistor of one of the
driving gates is in saturation and all others are cut-off. Corresponding to this
the output voltage at Y is VCE,sat » 0.2 V, which means the input diodes of all
the load gates driven from this combination are conducting. Assuming all the
other inputs of load gates to be HIGH.
IL = 0.82 mA
Assuming T1 to be in saturation, the collector current of T1 is given by,
N¢ IL + MI¢1
where, N¢ is the fan-out with the wire-ANDed connection. This collector cur-
rent must be same as the collector current of the single gate driving N gates
which is given by
NIL + I¢1
NIL + I¢1 = N¢IL + MI¢1
VCC(5 V) VCC(5 V)
RC
I¢1 Y1 Y
T1
IL
R
P1
T2
IL
R
P2
VCC
RC
I¢1
Y2
VCC
TM
IL
R
PN¢
VCC
YM
VCC
I¢1RC
Fig. Prob. 4.7
M Gates wire-ANDed N¢ Load gates

33
or N¢ = N – (M – 1) I¢1/IL = N – (M – 1) 2 182
0 82
.
.
= N – 2.66 (M – 1)
4.8 When all the inputs are HIGH, the input diodes are non-conducting. If we
assume that the transistor T1 is in saturation, then
VP = VBE, sat + VD + VBE, sat = 0.8 + 0.7 + 0.8 = 2.3 V
The voltage at the collector of T1
= VCE, sat + VD + VBE, sat
= 0.2 + 0.7 + 0.8 = 1.7 V
Since the voltage at P is higher than the voltage at the collector of T1, IB1 can-
not exist, therefore, the assumption that T1 is in saturation is inconsistent.
Hence T1 is in active region. In fact when T1 is conducting, the voltage drop
across R2 will reverse-bias the C-B junction of T1 and therefore T1 will defi-
nitely be operating in active region.
4.9 If any input is LOW, the corresponding input diode conducts and therefore,
VP = 0.9 V, which keeps T1, D2, and T2 cut-off. Hence Y = 1.
If all the inputs are HIGH, the input diodes will be nonconducting. T1 will be
in active region and T2 in saturation region. Hence Y = 0. This shows that the
circuit operates as a NAND gate.
(a) When all the inputs are HIGH,
VP = VBE1 + VD + VBE3, sat
= 0.7 + 0.7 + 0.8 = 2.2 V
Here, VBE has been assumed to be 0.7 V in active region. Therefore,
VCC – VP = R1I1 + R2IB1
Also I1 = (1 + hFE) IB1
IB1 =
−
× +
× =
5 2 2
1 75 31 2
10 49 783
.
.
. µA
and I1 = 1.543 mA, I2 =
VBE2
5
,sat
= 0.16 mA,
IB2 = I1 – I2 = 1.543 – 0.16 = 1.383 mA
Standard load =
− −
+
V V V
R R
CC D CE,sat
1 2
=
− −
+
=
5 0 7 0 2
1 75 2
1 093
. .
.
. mA
IC2 = ⋅ +
−
= +N I
V V
R
NL
CC CE
C
,
. .
sat
1 093 2 182

34
For T2 to be in saturation, IC2 £ hFE IB2
or, 1.093 N + 2.182 £ 30 ´ 1.383
or, N < 36
Therefore, the fan-out of this gate is 35 which is much higher than the fan-
out of the DTL gate of Fig. 4.12.
(b) Noise margins
D1 = 0.5 + 0.6 + 0.5 – 0.9 = 0.7 V
D0 = –V(1) + (VP – VDg)
= – 5 + (2.2 – 0.6) = – 3.4 V
(c) When the output is LOW, the power
P (0) = (I1 + I¢1) VCC
= (1.543 + 2.182) ´ 5
= 18.625 mW
When the output is HIGH, the power
P (1) = I1 ´ Vcc = 1.093 ´ 5 = 5.465 mW
The average power Pav =
+P P( ) ( )0 1
2
=
+
=
18 625 5 465
2
12 045
. .
. mW
4.10 (a) When at least one of the inputs is LOW,
VP = V (0) + VD = 0.2 + 0.7 = 0.9 V
Corresponding to this T1 and T2 will be nonconducting. When all the inputs
are HIGH, T1 will be conducting in active region, Zener will be in the
breakdown region and T2 in saturation. Therefore,
VP = VBE, active + VZ + VBE, sat
= 0.7 + 6.9 + 0.8 = 8.4 V
The 1 level noise margin = D1 = Vg + VZ + Vg – VP
= 0.5 + 6.9 + 0.5 – 0.9
= 7 V
The 0 level noise margin = D0 = – [V (1) – (VP – VDg)]
= – [15 – (8.4 – 0.6)]
= – 7.2 V
(b) When all the inputs are HIGH, VP = 8.4 V. Writing KVL from VCC to VP,
VCC – VP = R1 (1 + hFE) IB1 + R2 IB1

35
or, IB1 =
−
+ +
=
−
+
V V
R h R
CC P
FE1 21
15 8 4
3 41 12( )
.
( )
= 0.0489 mA
The current through Zener diode, I1 = 41 ´ 0.0489 = 2.004 mA
IB2 = I1 – I2 = 2.004 – 0.16 = 1.844 mA
The current through RC = =
14 8
15
0 9867
.
. mA
The load current IL = 0.95 mA
IC2 = 0.9867 + 0.95 N £ 40 ´ 1.844
or, N £ 76
(c) P(0) = (I1 + I¢1) ´ VCC
= (2.004 + 0.9867) ´ 15 = 44.86 mW
P(1) = I1 ´ VCC = 0.94 ´ 15 = 14.1 mW
Pav = 29.48 mW
4.11 IL = 0.94 mA, I¢1 = 0.9867 mA
N¢ = N – (M – 1) I¢1/IL
= N – 1.03 (M – 1)
4.12 The noise margins depend upon temperature because the voltage across a
conducting diode and VBE are temperature dependent. The input diode and the
base-emitter junction of T1 are in polarity opposition, therefore, the tempera-
ture sensitivities of these two junctions cancel. Therefore, the temperature
sensitivity of the circuit depends on the temperature sensitivities of D2 and the
base-emitter junction of T2. In HTL, D2 is replaced by the Zener diode. Since
the temperature sensitivity of a Zener diode is positive whereas for a forward-
biased diode it is negative, therefore, the temperature sensitivities of Z and the
base-emitter junction of T2 cancel (their magnitudes are of the same order).
Hence the temperature sensitivity of the HTL gate is significantly better than
that of the DTL gate.
4.13 (a) When the output is LOW.
Base-collector junction of T1 is forward-biased T2 and T3 are in saturation.
Therefore, VB1 = 0.7 + 0.8 + 0.8 = 2.3 V
Current through RB1 =
−
=
5 2 3
4
0 675
.
. mA
VC2 = 0.8 + 0.2 = 1V
Current through RC2 =
−
=
5 1
1 4
2 857
.
. mA

36
Since, T4 and D are cut-off, therefore, IC4 = 0
Therefore,
ICC(0) = 0.675 + 2.857
= 3.532 mA
(b) At least one of the inputs is LOW.
VB1 = 0.2 + 0.7 = 0.9
T2, T3 and T4 are cut-off
ICC1 = Current through RB1 =
−5 0 9
4
.
= 1.025 mA
(c) The total current will be sum of current through RB1 (as given in (b) part
above) and given in Eqs. 4.10 and 4.11
= 1.025 + 41.36
= 42.385 mA
4.14 The current I remains same and it does not affect the fan-out of the gate G1.
4.15 (a) If RC4 = 0, the change in output from logic 0 to logic 1 will be faster. Since
T3 does not turn off (because of storage time) as quickly as T4 turns on,
therefore, both T3 and T4 will be conducting simultaneously for some time
which will cause almost short circuiting of the VCC supply.
(b) When the output is in LOW state, VB4 = 1 V which makes VBE4 = 0.8 V if
the diode D is not present. This means T4 will be in saturation and its
collector current would be
IC4 =
− −V V VCC CE CE4 3
100
, ,sat sat
=
− −
=
5 0 2 0 2
100
46
. .
mA
which is very large and will increase significantly the power dissipation.
Moreover, it is simply a wastage of power.
(c) (i) When output is in LOW state, the shorting of output to ground will not
have any effect.
(ii) When output is in HIGH state, the relevant portion of the circuit with
output shorted to ground is shown in Fig. Prob. 4.15. The base current
and the collector current of T4 will become
IB4 =
− −V V V
R
CC BE D
C
4
2
,sat
=
− −
=
5 0 8 0 7
1 4
2 5
. .
.
. mA

37
and IC4 =
− −V V V
RC
CC CE D4
4
,sat
=
− −
=
5 0 2 0 7
100
41
. .
mA
Is = IC4 + IB4
= 41 + 2.5 = 43.5 mA
This large current will continuously be drawn from the supply as long as at
least one of the inputs is LOW. This will damage the transistor T4 and the
diode D.
VCC = 5V
Is
RC2 = 1.4 kW
RC4 = 100 kW
IC4
T4
IB4
DC2
E3
C3
E2
Fig. Prob. 4.15
4.16 Let the output transistor T3 of one gate is in saturation, while that of the other
gate is cut-off. The voltage at Y will be LOW, which will make the transistor
T4 of the gate whose T3 is cut-off to conduct through T3 of the other gate which
is in saturation. The corresponding current drawn from the power supply will
be IC4 + IB4 = 41.4 mA. This continuous current will damage these transistors.
When both the outputs are HIGH or LOW, the currents drawn from the
supply will be same as the currents without this connection.
4.17 The circuit is shown in Fig. Prob. 4.17.
RC(max) =
−
+
=
− ×
+ ×
V V
I I
CC OH
OH IH8
5 2 4 10
250 8 40
3( . )
kW
= 4.56 kW
RC(min) =
−
+
=
−
− ×
=
V V
I I
CC OL
OL IL8
5 0 4
16 8 1 6
1 44
.
.
. kW
Therefore, 1.44kW < RC < 4.56 kW
4.18 The relevant portion of the circuit is given in Fig. Prob. 4.18.
(i) When the output Y = 1,
VCC – (5 IOH + 6 IIH) RC ³ VOH

38
which gives
RC(max) =
−
+
=
− ×
× + ×
=
V V
I I
CC OH
OH IH5 6
5 2 4 10
5 250 6 40
1 74
3( . )
.k kW W
VCC = +5 V
RC
IIH
IOH
Output circuit
of open-collector
gate
Load gates
VCC = 5 V
RC
IOL
IIH
IIL
IIH
IIL
IIH
IIL
IIH
IIL
IIH
IIL
IIH
IIL
IOH
IOH
IOH
IOH
IOH
Y
Fig. Prob. 4.17
Fig. Prob. 4.18

39
(ii) When the output Y = 0, it is assumed that only one of the driving gates has
its output transistor in saturation while the output transistors of all the other
gates are cut-off.
V V
R
CC OL
C
−
£ IOL + NIIL
which gives
RC(min) =
−
+
V V
I NI
CC OL
OL IL
=
−
− ×
≈
5 0 4
16 6 1 6
0 72
.
.
. kW
Therefore, RC should be between 0.72 kW and 1.74 kW. A value of RC = 1 kW
is reasonable.
4.19 Let us assume a supply voltage VCC = + 5V and corresponding VOH = 2.4 V
RC(max) =
− ×
× + ×
≈
( . )
.
5 2 4 10
7 250 7 40
1 28
3
kW
and RC(min) =
−
− ×
≈
5 0 4
40 7 1 6
0 159
.
.
. kW
Therefore, 0.159kW < RC < 1.28 kW
4.20 (a) No (b) No (c) No (d) Yes
A 7407
VCC = +5 V VCC = +10 V
10 V, 30 A
Lamp
7407 is an open-collector non-inverting buffer with VOH = 30V (maximum),
which means a lamp load along with the necessary supply voltage may be
connected as shown in Fig. Prob. 4.20.
4.21 Let us take ALS devices driving other devices.
(i) ALS driving standard devices
IOH (ALS) = – 400 mA
IOL (ALS) = 8 mA (74 series)
IIH (Standard) = 40 mA
IIL (Standard) = – 1.6 mA
Fig. Prob. 4.20

40
Here, – IOH (ALS) = 10 ´ IIH (Standard)
and – IOL (ALS) = 5 ´ IIL (Standard)
This means, when the output is LOW, the fan-out is 5, whereas it is 10
when the output is HIGH. Therefore, the fan-out is 5
(ii) ALS driving ALS
IIH (ALS) = 20 mA
IIL (ALS) = – 0.1 mA
Which gives a fan-out of 20 when the output is HIGH and 80 when it is
LOW. Therefore, the fan-out is 20.
Similarly, the complete table can be verified.
4.22 Case I
Let T2 be cut-off. Then the output circuit will appear as shown in Fig.
Prob. 4.22(a), whose equivalent circuit is shown in Fig. Prob. 4.22(b).
RC2
P
T4
Y
RE4
Q
Vn
RC2
Y
RE4
Q
Vn
C4
P
B4
I E4
(a) (b)
From the equivalent circuit, we obtain
(a) VYQ =
+
+ +
R h
R h R
VE FE
C FE E
n
4
2 4
1
1
( )
( )
=
+
1 5 101
0 3 101 1 5
. ( )
. ( ) ( . )
Vn
= 0.998 Vn
(b) VYP = – (Vn – VYQ) = – 0.002 Vn
Therefore, if the terminal P is grounded, the noise voltage present in the
output is negligibly small.
Case II
Let T2 be conducting and T1 be cut-off.
(a) The noise voltage at the collector of T2 = the noise voltage at the base of
T4.
=
+
=1 18
1 18 0 3
0 797.
. .
. .V Vn n
Since T4 is operating as an emitter-follower, therefore,
VYQ = 0.797 Vn
(b) VYP = – (Vn – 0.797 Vn) = – 0.203 Vn
hFE I
Fig. Prob. 4.22

41
This again shows that the noise voltage is very small between Y and P
and hence the terminal P is grounded.
4.23 (a) The 5.2 V supply will appear across RE4 or RE3 and no damage is caused to
the supply and the circuit.
(b) The 5.2 V supply voltage will appear across the output transistor T4 or T3.
Also 5.2 V supply gets applied to their bases through RC2 and RC1 respec-
tively. Therefore, the output transistor will burn out.
4.24 In a TTL gate, when the output changes from V(0) to V(1), a current spike of
41.4 mA is produced, whereas in the case of ECL the change in current is
negligibly small when the output changes from LOW to HIGH and vice-versa.
4.25 Let A = B = C = 0, D = 1, and E = 0
Therefore, Y1 = 0 and Y2 = 1.
Corresponding to this T4 of G1 is acting as an emitter follower while that of
G2 is acting as a diode. The relevant portions of the circuits are shown in Fig.
Prob. 4.25. In this when Y1 and Y2 are connected together, the voltage at the
output terminal will be equal to – 0.75 V (i.e., the voltage across T4 acting as
a diode). Consequently T4 goes to cut-off. Similarly, when Y1 = 1 and Y2 = 0
identical situation will prevail making the output 1. When Y1 and Y2 both are
same, the output will be equal to Y1 = Y2. This confirms that OR operation is
performed when the outputs are connected in wired logic. Similarly, it can be
proved for all the other cases.
RC2
T4
RE4
Y1
Y2
-5.2 V
(-0.85 V)
VCC = 0 VCC = 0
RC2
T4
(-0.75 V)
RE4
-5.2 V
(-1.55 V)
4.26 The output logic levels of ECL, input/output logic levels of MC10H125 IC,
and the input logic levels of TTL are shown in Fig. Prob. 4.26
Fig. Prob. 4.25
2.5V VOH
0.5V VOL
–1.13V VIH
–1.48V VIL
MC10H125
Translator
2V VIH
0.8 VIL
TTL
VOH–0.9V
–1.7V VOL
ECL
(a) Output logic level
voltages of ECL
(b) Input/output logic
level voltages of
Translator
(c) Input logic level
voltages of TTL
Fig. Prob. 4.26

42
From the logic levels, we observe,
VIH (Translator) < VOH (ECL)
VIL (Translator) > VOL (ECL)
which shows that the input of MC10H125 IC is ECL compatible.
Similarly,
VIH (TTL) < VOH (Translator)
VIL (TTL) > VOL (Translator)
which shows that the output of the translator is compatible with TTL.
4.27 The output Y of ECL NOR gate is Y = A B+
The output of the Translator circuit is Y and the output of TTL Inverter will
be Y = Y.
A
B
Y
Y
Y
ECL TTLMC10H125
Translator
Fig. Prob. 4.27
The complete circuit is shown in the above figure.
4.28 (a) Consider the NMOS inverters shown in Fig. 4.25. If the output accidently
gets shorted, large current from VDD will continuously flow through the
load transistor T2 which may damage the load transistor.
(b) Consider the CMOS inverter of Fig. 3.33. When T1 is ON, the output
voltage is LOW (» 0V). Now if the output gets shorted to ground, it does
not cause any problem. On the other hand when Vi is LOW, T1 is cut-off,
and if the output gets shorted to ground, whole of VCC will appear across
T2 which is conducting. This will cause a relatively very high current to
flow through T2 which may damage it, since T2 is not meant to carry such
large currents. The normal current through T1 and T2 is extremely small
being the OFF current of either T1 or T2.
4.29 Its operation is given below
Inputs State of Output
A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON VCC
0 VCC ON OFF OFF ON 0
VCC 0 OFF ON ON OFF 0
VCC VCC ON ON OFF OFF 0

43
4.30 The fan-out is given below.
TTL/CMOS 74HC 74HCT 74AC 74ACT
54/74 400 400 400 400
54H/74H 500 500 500 500
54L/74L 200 200 200 200
54S/74S 1000 1000 1000 1000
54LS/74LS 4000 4000 4000 4000
54AS/74AS 2000 2000 2000 2000
54ALS/74ALS 400 400 400 400
4.31
54/74 54H/74H 54L/ 54S/ 54LS/ 54AS/ 54ALS/
74L 74S 74LS 74AS 74ALS
(a) 74HC/74HCT 2 2 21 2 11 8 40
(b) 74 AC/74 ACT 15 12 133 12 66 48 240
4.32 When output is HIGH, it can drive a total of up to 1200 gates.
When output is LOW, it can drive 20 74AS gates requiring 10 mA of current.
The remaining 14 mA of current can drive 140 74ALS gates. Therefore, max-
imum possible number of ALS gates which can be driven is 140.
4.33 The output logic levels of CMOS and the input logic levels of MC10H124
TTL-to-ECL translator are given in Fig. Prob. 4.33.
Fig. Prob. 4.33
From these logic levels, we observe,
VIH (Translator) < VOH (CMOS)
VIL (Translator) > VOL (CMOS)
which shows that the input of the translator is compatible with CMOS. Since
the output of the translator is compatible with ECL, therefore, CMOS-to-ECL
interfacing is possible using TTL-to-ECL translator.
4.34 The output logic levels of MC10H125 translator and the input logic levels of
CMOS (74HCT & 74 ACT) are shown in Fig. Prob. 4.34.
CMOS MC10H124
translator
VOH 3.76V
VOL 0.37V
VIL 0.8V
2VVIH
(a) (b)

44
Fig. Prob. 4.34
From these logic levels, we observe,
VIH (CMOS) < VOH (Translator)
VIL (CMOS) > VOL (Translator)
Therefore, the output of the translator is compatible with these CMOS devices.
Since the input of the translator is compatible with ECL, therefore, ECL-to-
CMOS interfacing is possible.
For CMOS 74 HC, and 74 AC series
VIL = 1.35V
VIH = 3.85V
and for CMOS 74 C series
VIL = 1.5V
VIH = 3.5V
For these CMOS ICs, VIL (CMOS) > VOL Translator
but VIH (CMOS) < VOH (Translator)
Therefore, a resistance R and VCC are required to be connected to pull up the
voltage at P corresponding to VOH (Translator)
MC10H125
Translator
CMOS
(74HCT & 74ACT)
(a) (b)
VOH 2.5V
VOL 0.5V
VIL 0.8V
2VVIH
VCC
P
R
MC10H125
Translator
CMOS
(c)
Fig. Prob. 4.34

45
CHAPTER 5
5.1 Let S1 and S2 be the two switches. The circuit diagram of the system is shown
in Fig. Prob. 5.1(a):
S1
S2
L
0 1
L
0 1
S1 S2
Bulb
Supply
ON = 1
OFF = 0
(a) The truth table is given below:
S1 S2 L
0 0 0
0 1 1
1 0 1
1 1 0
(b) The logic equation is
L = S1 S2 + S1 S2
(c) The AND-OR realization is given in Fig. Prob. 5.1(b):
Fig. Prob. 5.1(a)
Fig. Prob. 5.1(b)
(d) Replace each of the AND gates and the OR gate in the above figure by
NAND gates. The resulting circuit will be NAND-NAND realization.
5.2 (a) Inputs Output
A B C D f
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
(Contd.)

46
(Contd.)
Inputs Output
A B C D f
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
(b) The K-map is given in Fig. Prob. 5.2.
The simplified expression is f = BC + BD
5.3 (a) f1 = (A + B + C + D ) ( A + B + C + D) (A + B + C + D)
(A + B + C + D) (A + B + C + D ) (A + B + C + D)
(A + B + C + D) (A + B + C + D) (A + B + C + D )
f2 = (A + B + C + D) (A + B + C + D) (A + B + C + D )
(A + B + C + D) (A + B + C + D) (A + B + C + D)
(A + B + C + D ) ( A + B + C + D ) (A + B + C + D)
(b) The K-maps for f1 and f2 are given in Fig. Prob. 5.3(a) and (b) respectively.
The minimized expressions are:
B
C
D
B
BD
BC
AB
CD 00 01 11 10
1 1
1 1
1 1
00
01
11
10
f
(a)
(b)
Fig. Prob. 5.2
AB
CD 00 01 11 10
00
01
11
10
0 0 0
0 0
0 0
0 0
AB
CD 00 01 11 10
00
01
11
10
0
0 0 0
0 0 0
0 0
(a) (b)
Fig. Prob. 5.3

47
f1 = (B + C + D) (A + B + C) (A + B + D) (A + B + D) (A + B + C )
f2 = (A + C ) (A + B) (A + C + D ) (B + D )
(c) The OR-AND realizations are shown in Fig. Prob. 5.3(c) and (d) for f1 and
f2 respectively.
(d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to
obtain realizations using only NOR gates.
5.4
(a)
C
A
C
B
A
D
B
A
B
D
B
C
A
A
A
B
B
C
D
D
A
C
f1
B
D
f2
(c) (d)
Fig. Prob. 5.3
A
B
C
D
B
C
B
D
D
A
A
B
f
Fig. Prob. 5.4(a)

48
(c) Realization for (a) requires
7400 – 1
7420 – 1/2
7430 – 1
a total of three chips.
Realization for (b) requires
7427 – 1
74260 – 1
a total of only two chips.
5.5 (a)
A
B
C
A
B
C
B
A
D
A
B
D
f
D
(b)
Fig. Prob. 5.4(b)
A
C
A
C
D
B
7410
Y
B
A
C
A
B
C
B
D
C
7427
1/3 7427
Y
(b)
Fig. Prob. 5.5

49
(c) Realization of (a) requires only one chip whereas (b) requires two chips.
5.6
A
D
D
C
B
f
3/4 7402
5.7 (a)
1 1
1 1
1 1 1 1
1 1 1 1
00 01 11 10
00
01
11
10
AB
CD
A
C
A
B
f
Fig. Prob. 5.6
(b) f = å m (2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
(c) f = A + C
Fig. Prob. 5.7(a)
5.8 (a) Figure Prob. 5.8 (i) below gives the K-map. Using offset adjacencies shown
in the K-map, the expression for f1 can be written as
f1 = (C ¤ D) (A ¤ B) + (C ⊕ D) (A ⊕ B)
= (A ⊕ B) ¤ (C ⊕ D)
1 1
1 1
1 1
1 1
00 01 11 10
00
01
11
10
AB
CD
C D (A ¤ B)
C D (A Å B)
CD (A ¤ B)
CD (A Å B)
Fig. Prob. 5.7(b)
Fig. Prob. 5.8(i)

50
A
B
C
D
f1
Logic 1
Fig. Prob. 5.8(ii)
Its realization using EX-OR gates is given in Fig. Prob. 5.8(ii). This real-
ization requires only one 7486 IC chip.
(b) Its K-map is given in Fig. Prob. 5.8(iii)
The minimized expression is
f2 = A B + ABD + ACD
The realization using NAND gates is given in Fig. Pro. 5.8(iv). This re-
quires one 7410 chip and one gate of 7400 chip.
1 1
1
1 1 1
1 1
00 01 11 10
00
01
11
10
AB
(iii)
CD
(iv)
A
B
B
D
A
C
D
A
f2
Fig. Prob. 5.8
5.9 Truth table of BCD-to-Excess-3 code converter is given below.
BCD Excess-3
D C B A E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Here only ten out of sixteen combinations are used and the other six are
taken as don’t-care conditions. The K-maps for the outputs E0, E1, E2 and
E3 are given in Fig. Prob. 5.9. The minimized expressions are:
E0 = A

51
00
01
11
10
DC
BA 00 01 11 10
0 1 ´ 0
1 0 ´ 1
1 0 ´ ´
1 0 ´ ´
00
01
11
10
DC
BA 00 01 11 10
0 0 ´ 1
0 1 ´ 1
0 1 ´ ´
0 1 ´ ´
E2 E3
(c) (d)
00
01
11
10
00 01 11 10
1 1 ´ 1
0 0 ´ 0
0 0 ´ ´
1 1 ´ ´
00
01
11
10
BA 00 01 11 10
1 1 ´ 1
0 0 ´ 0
1 1 ´ ´
0 0 ´ ´
E0 E1
(a) (b)
DC
BA
DC
E1 = BA + B A
E2 = CBA CA CB+ +
E3 = D + CA + CB
The circuit can be drawn using NAND gates.
5.10 Truth table of Excess-3-to-BCD converter can be prepared using the truthtable
of Prob. 5.9. The K-maps can then be prepared and minimized. The minimized
expressions are given below.
A = E0
B = +E E E E1 0 1 0
C = E E2 1 + E2 E1 E0 + E3 E1 E0
D = E3 E2 + E3 E1 E0
The circuit can now be drawn using NAND gates.
5.11 (a) The K-map is shown in Fig. Prob. 5.11(a). The minimized expression is
f C D C D1 = = +
(b) The K-map is shown in Fig. Prob. 5.11(b). The minimized expression is
f A B D B C D A C2 = + + + + +( ) ( ) ( )
(c) The K-map is shown in Fig. Prob. 5.11(c). The minimized expression is
f A B C D B C D A B C A C D3 = + + + + + + + + +( ) ( ) ( ) ( )
The circuits for f1, f2, and f3 can be drawn using NOR gates.
Fig. Prob. 5.9

52
00
01
11
10
AB
CD 00 01 11 10
0 0 0 0
0 0 0 0
0 0 0 0
00
01
11
10
AB
CD 00 01 11 10
0
0 0
0 0
0 0 0
(a) (b)
0 0
0
0
0 0
(c)
00
01
11
10
AB
CD 00 01 11 10
5.12 The K-map for f1 is shown in Fig. Prob. 5.12 and the minimized expression is
f ABE ACE ABD BC ABCDE1 = + + + +
This can be realized using NAND gates.
Similarly, the minimized expression for f2 is
f CE ABD ADE ADE BCE CDE ABE2 = + + + + + +
which can be realized using NAND gates.
00
01
11
10
00 01 11 10
1
1 1
1 1
1
BC
DE 00 01 11 10
BC
DE
00
01
11
10
A = 0
ABD
A = 1
ABE BC
AC EAB C D E
1 1
1
1 1
1 1 1
Fig. Prob. 5.11
Fig. Prob. 5.12
5.13 (a) Its K-map is given in Fig. Prob. 513(a).

53
00
01
11
10
00 01 11 10
0
1 1 0 1
0 0
1 1 0 0
AB
CD
A
C
D
B
C
D
D
C
A
Y
(a)
The minimized expression is
Y ACD BCD ACD= + +
Fig. Prob. 5.13(a)
C
D
D
C
Y
(b) The K-map is given in Fig. 5.18 of the book and Y CD CD= +
(c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one
IC chip (7400) only is required.
Fig. Prob. 5.13(b)
5.14 (a) Figure Prob. 5.14(a) and (b) show the K-maps of f1 for NAND and NOR
realizations respectively. The minimized expressions are
f1 = + + +ABC CD BD AD (SOP)
and f1 = + + + + +( ) ( ) ( ) ( )A B C C D B D A D (POS)
Circuits using NAND and NOR gates can be designed using the above
expressions.
(b) Similar to part (a), the minimized expressions are obtained which are given
below.
f2 = + +AC D BC AB (SOP)
Fig. Prob. 5.13(c)

54
and f2 = + + + +( ) ( ) ( ) ( )A B B D B C A C (POS)
These equations can be used to design circuits with NAND and NOR gates.
00 01 11 10CD
AB
1
1 1 ´ 1
1 1 1
´
(a)
00
01
11
10
AB
CD
00 01 11 10
0 0 0
´
0
´ 0 0 0
(b)
00
01
11
10
00
01
11
10
00 01 11 10
1
1 1 1
1
1 1 1
CD
AB
B
C
A
A
C
D
A (B Å C)
A(C Å D)
CD
00
01
11
10
AB
00 01 11 10
1 1
1 1
A
B
D
C
f1
AC (B ¤ D)
A C (B Å D)
(b)
f2
5.15 Its K-map and circuit realization are given in Fig. Prob. 5.15.
(a)
Fig. Prob. 5.14

55
(c)
00
01
11
10
00 01 11 10CD
AB
1
1
1
1
A C(B Å D)
AC (BÅD)
A
C
B
D
f3
5.16 Its truth table is given in Table Prob. 5.16.
Table Prob. 5.16
4-bit word Odd parity bit Even parity bit
A B C D PO PE
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0
The K-map for Po is given in Fig. Prob. 5.16(a), from which Po is obtained as
Po = AC (B ¤ D) + AC (B Å D) + AC (B Å D) + AC (B ¤ D)
= (A Å C) ¤ (B + D)
Its realization using EX-OR and EX-NOR gates is given in Fig. Prob. 5.16(b).
Fig. Prob. 5.15
00
01
11
10
00 01 11 10
1 0 1 0
0 1 0 1
1 0 1 0
0 1 0 1
AB
CD
(a)
A
C
B
D
Po
(b)
Fig. Prob. 5.16

56
5.17 From the truthtable given in Prob. 5.16, K-map is prepared and the circuit is
designed. These are given in Fig. Prob. 5.17.
PE = A ⊕ B ⊕ C ⊕ D
00
01
11
10
00 01 11 10
1 1
1 1
1 1
1 1
AB
CD
(a) (b)
A
B
C
D PE
Fig. Prob. 5.17
5.18(a) The K-map using 1’s is given in Fig. Prob. 5.18(a). The minimized expres-
sion for f1 is
f ABC DE ABCDF CEF A BC DEF1 = + + +
The circuit for f1 can be realized using NAND gates.
Similarly, we can minimize using 0’s which will lead to a circuit realizable
by NOR gates.
(b) The K-map using 0’s is given in Fig. Prob. 5.18(b). The minimized expres-
sion for f2 is
f2 = (A + B + C + D + E + F ) ( A + B + D + E + F)
(A + B + C + E + F ) (A + C + D + E + F)
(A + B + C + E + F) (A + B + C + E + F)
(A + B + C + E + F) (A + B + C + D)
(A + B + D + E) (B + C + D + E)
(B + C + D + F ) (A + B + C + D)
The circuit for f2 can be realized using NOR gates. Similarly, we can minimize
the function using 1s which will lead to a circuit realizable by NAND gates.
5.19 Let the augend, addend, and the carry inputs to the full-adder be An, Bn, and
Cn – 1 respectively and Sn, and Cn be the sum and carry outputs respectively.
(a) An and Bn are applied at the two inputs of first half-adder HA – 1.
Its outputs are S1 (Sum) and C1 (Carry). Its truth table is given in Table
Prob. 5.19.
Table Prob. 5.19(a)
An Bn S1 C1
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

57
A
B
00
01
11
10
00 01 11 10
1 1
1
CD
EF
0 1
0
ABCDEF
00 01 11 10
1 1
CD
EF
00
01
11
10
00 01 11 10
1 1
1 1
1
CD
EF
1
00 01 11 10
1 1
CD
EF
00
01
11
10
00
01
11
10
ABCDF
00
01
11
10
00 01 11 10
CD
EF
0
00 01 11 10
0 0
0
0 0
0
CD
EF
00
01
11
10
0 1
0 0 0
0 0
0
0
00 01 11 10
CD
EF
1
00 01 11 10
CD
EF
00
01
11
10
0 0
0 0 0
0
0 0
00
01
11
10
CEF
ABC DE
A
B
Fig. Prob. 5.18(b)
Fig. Prob. 5.18(a)

58
Fig. Prob 5.19(a)
HA – 1
HA – 2
S1
C1
BnAn Cn – 1
C2
S2 = Sn
Cn
Truth table of the full-adder using input variables S1, C1, and Cn – 1 is given
below:
Table Prob. 5.19(b)
C1 S1 Cn – 1 Cn Sn
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
0 0 1 0 1
0 1 1 1 0
1 0 1 1 1
K-maps for Cn and Sn are shown below:
0 0 ´ 1
0 1 ´ 1
0
1
0 0 1 ´ 0
1 1 0 ´ 1
K-map for Cn K-map for Sn
Cn – 1
C1
00 01 11 10
S1
Cn – 1
C1 S1
00 01 11 10
Cn = C1 + S1 × Cn – 1 Sn = S1 Cn -1 + S1 Cn – 1
= C1 + C2 = S1 Å Cn – 1
Sn and Cn are generated using HA –2 and an OR gate as shown in the block
diagram.

59
(b) EX–OR(1)
An
Bn
C1
S1
AND–1
EX–OR(2)
S2 = Sn
AND-2
C2
Fig. Prob. 5.19(b)
Cn–1
5.20 Propagation delay time for Sn
= tpd [EX-OR(1)] + tpd [EX –OR(2)]
= 20 + 20 = 40 ns.
Propagation dealy time for Cn
= tpd [EX-OR(1) + tpd (AND-2) + tpd(OR)
= 20 + 10 + 10 = 40 ns.
Since the propagation delay time (tpd) of AND–1 is less than the tpd of
EX-OR(1), therefore, it is not counted.
5.21 f(A, B, C, D) = pM(2, 7, 8, 9, 10, 12)
= Sm (0, 1, 3, 4, 5, 6, 11, 13, 14, 15)
Table (a) Grouping of minterms according to number of 1’s.
Group Minterm Variables Check for inclusion
A B C D in groups of 2
0 0 0 0 0 0 ü
1 1 0 0 0 1 ü
4 0 1 0 0 ü
3 0 0 1 1 ü
2 5 0 1 0 1 ü
6 0 1 1 0 ü
11 1 0 1 1 ü
3 13 1 1 0 1 ü
14 1 1 1 0 ü
4 15 1 1 1 1 ü
Table (b) Grouping of two minterms
Group Minterms Variables Check for inclusion
A B C D in groups of 4
0 0, 1 0 0 0 — ü
0, 4 0 — 0 0 ü
1, 3 0 0 — 1
1, 5 0 — 0 1 ü
(Contd.)
Cn
OR

60
(Contd.)
A B C D in group of 4
1 4,5 0 1 0 — ü
4, 6 0 1 — 0
3, 11 — 0 1 1
2 5,13 — 1 0 1
6, 14 — 1 1 0
11, 15 1 — 1 1
3 13, 15 1 1 — 1
14, 15 1 1 1 —
Table (c) Grouping of 4 minterms
Group Minterms Variables
A B C D
0 0, 1, 4, 5 0 — 0 —
0, 4, 1, 5 0 — 0 —
Table (d) PI table
PI Decimal Minterms
terms numbers 0 1 3 4 5 6 11 13 14 15
A C ü 0, 1, 4, 5 Ä ´ ´ ´
A B D ü 1, 3 ´ ´
A B D ü 4, 6 ´ ´
B C D ü 3, 11 ´ ´
B C D ü 5,13 ´ ´
B C D ü 6, 14 ´ ´
A C D ü 11, 15 ´ ´
ABD 13, 15 ´ ´
ABC 14, 15 ´ ´
ü ü ü ü ü ü ü
From the PI table, we see that the column for minterms 0 contains only one
´, therefore, A C is an essential prime-implicant. All the other columns con-
tain 2 or more Xs. Therefore, starting from the prime-implicant A B D, we see
the minterms that are covered by each prime-implicant and find the minimum
number of prime-implicants that will cover all the minterms. Depending upon
the prime-implicants selected above, the minimized function is
f(A, B, C, D) = AC ABD ABD BCD BCD BCD+ + + + + + ACD
There can be other options also.

61
5.22 f (A, B, C, D) = Sm (1, 3, 5, 8, 9, 11, 15) + d(2, 13)
Table (a) Grouping of minterms/don’t care terms according to number of 1’s.
Group Minterm/ Variables Check for inclusion
don’t care term A B C D in group of 2
1 0 0 0 1 ü
1 2* 0 0 1 0 ü
8 1 0 0 0 ü
3 0 0 1 1 ü
2 5 0 1 0 1 ü
9 1 0 0 1 ü
11 1 0 1 1 ü
3 13* 1 1 0 1 ü
4 15 1 1 1 1 ü
Table (b) Grouping of 2 minterms/don’t care terms
Group Minterms/ Variables Check for inclusion
don’t care terms A B C D in group of 4
1, 3 0 0 — 1 ü
1, 5 0 — 0 1 ü
1 1, 9 — 0 0 1 ü
2*, 3 0 0 1 —
8, 9 1 0 0 —
3, 11 — 0 1 1 ü
5, 13* — 1 0 1 ü
2 9, 11 1 0 — 1 ü
9, 13* 1 — 0 1 ü
3 11, 15 1 — 1 1 ü
13, 15 1 1 — 1 ü
Table (c) Grouping of 4 minterms/don’t care terms
Group Minterms/ Variables
don’t care terms A B C D
1, 3, 9, 11 — 0 — 1
1 1, 5, 9, 13* — — 0 1
1, 9, 3, 11 — 0 — 1
1, 9, 5, 13* — — 0 1
9, 11, 13*, 15 1 — — 1
2 9, 13*, 11, 15 1 — — 1
There are a total of 5 prime-implicants BD, CD, and AD from Table (c) and
ABC and ABC from Table (b).

62
(Contd.)
Table (d) PI Table
PI Decimal Minterms/don’t care terms
terms numbers 1 2* 3 5 8 9 11 13* 15
BD 1, 3, 9, 11 ´ ´ ´ ´
CD 1, 5, 9, 13* ü ´ Ä ´ ´
AD 9, 11, 13*, 15 ü ´ ´ ´ Ä
ABC 2*, 3 ´ ´
ABC 8, 9 ü Ä ´
ü ü ü
The essential prime- implicants are: CD, AD, and ABC . Except the minterm
3 all the other minterms have heen covered by the essential prime-implicatns.
Therefore, BD is to be included in the minimized expression. The minimized
function is
f (A, B, C, D) = BD CD AD ABC+ + + .
5.23 f (A, B, C, D, E) = Sm (8, 9, 10, 11, 13, 15, 16, 18 , 21, 24, 25, 26, 27, 30, 31)
Table (a) Grouping of minterms according to number of 1’s
Group Minterm Variables Check for inclusion
A B C D E in group of 2
1 8 0 1 0 0 0 ü
16 1 0 0 0 0 ü
9 0 1 0 0 1 ü
2 10 0 1 0 1 0 ü
18 1 0 0 1 0 ü
24 1 1 0 0 0 ü
11 0 1 0 1 1 ü
13 0 1 1 0 1 ü
3 21 1 0 1 0 1
25 1 1 0 0 1 ü
26 1 1 0 1 0 ü
15 0 1 1 1 1 ü
4 27 1 1 0 1 1 ü
30 1 1 1 1 0 ü
5 31 1 1 1 1 1 ü
Table (b) Grouping of 2 minterms
8, 9 0 1 0 0 — ü
1 8, 10 0 1 0 — 0 ü

63
(Contd.)
Group Minterm Variables Check for circlusion
8, 24 — 1 0 0 0 ü
16, 18 1 0 0 — 0 ü
16, 24 1 — 0 0 0 ü
9, 11 0 1 0 — 1 ü
2 9, 13 0 1 — 0 1 ü
9, 25 — 1 0 0 1 ü
10, 11 0 1 0 1 — ü
10, 26 — 1 0 1 0 ü
18, 26 1 — 0 1 0 ü
24, 25 1 1 0 0 — ü
24, 26 1 1 0 — 0 ü
11, 15 0 1 — 1 1 ü
11, 27 — 1 0 1 1 ü
3 13, 15 0 1 1 — 1 ü
25, 27 1 1 0 — 1 ü
26, 27 1 1 0 1 — ü
26, 30 1 1 — 1 0 ü
15, 31 — 1 1 1 1 ü
4 27,31 1 1 — 1 1 ü
30, 31 1 1 1 1 — ü
Table (c) Grouping of 4 minterms
8, 9, 10, 11 0 1 0 — — ü
8, 9, 24, 25 — 1 0 0 — ü
8, 10, 9, 11 0 1 0 — — ü
1 8, 10, 24, 26 — 1 0 — 0 ü
8, 24, 9, 25 — 1 0 0 — ü
8, 24, 10, 26 — 1 0 — 0
16, 18, 24, 26 1 — 0 — 0
16, 24, 18, 26 1 — 0 — 0
9, 11, 13, 15 0 1 — — 1
9, 11, 25, 27 — 1 0 — 1 ü
9, 13, 11, 15 0 1 — — 1
9, 25, 11, 27 — 1 0 — 1 ü
2 10, 11, 26, 27 — 1 0 1 — ü
10, 26, 11, 27 — 1 0 1 — ü
24, 25, 26, 27 1 1 0 — — ü
24, 26, 25, 27 1 1 0 — — ü
11, 15, 27, 31 — 1 — 1 1
11, 27, 15, 31 — 1 — 1 1
3 26, 27, 30, 31 1 1 — 1 —
26, 30, 27, 31 1 1 — 1 —

64
Tabe (d) Grouping of 8 minterms
Group Minterms Variables
A B C D E
1 8, 9, 10, 11, 24, 25, 26, 27 — 1 0 — —
Tabe (e) PI Table
PI Decimal Minterms
terms numbers 8 9 10 11 13 15 16 18 21 24 25 26 27 30 31
ABCDE ü 21 Ä
ACE ü 16, 18, 24, 26 Ä ´ ´ ´
ABE ü 9, 11, 13, 15 ´ ´ Ä ´
BDE 11, 15, 27, 31 ´ ´ ´ ´
ABD ü 26, 27, 30, 31 ´ ´ Ä ´
BC ü 8, 9, 10, 11, 24, ´ ´ ´ ´ ´ Ä ´ ´
25, 26, 27
ü ü ü ü ü
The minimized function is
f(A, B, C, D, E) = ABCDE + ACE + A BE + ABD + BC

65
CHAPTER 6
6.1 (a) In the 16:1 multiplexer IC 74150, the data output is inverted input, i.e.,
complement of the data input line selected. Since the data output is 1 when
the input variables correspond to decimal numbers 2, 4, 6, 7, 9, 10, 11, 12
and 15, therefore, the data input lines corresponding to these decimal
numbers are to be connected to logic 0 and the data input lines 0, 1, 3, 5, 8,
13, and 14 are to be connected to logic 1. The circuit is shown in Fig.
Prob. 6.1.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
G
16:1
Multiplexer
74150
A B C D
Y
S3 S2 S1 S0
Logic 0
Logic 1
(MSB)
Logic 0
(LSB)
Fig. Prob. 6.1
(b) To realize a four variable truthtable or logic expression using an 8:1 multi-
plexer the truth table is partitioned as shown by dotted lines (Table 6.3). In
this, the inputs A, B, and C are to be connected to S2, S1, and S0
Table Prob. 6.1(b)
Inputs Output
A B C Y
0 0 0 0
0 0 1 D
0 1 0 D
0 1 1 1
1 0 0 D
1 0 1 1
1 1 0 D
1 1 1 D

66
select inputs respectively. Now, we observe the relationship between input
D and output Y for each group of two rows. There are four possible values
of Y and these are 0, 1, D, and D . These are given in Table Prob. 6.1(b).
From this table, we note the output Y for each of the combinations of A, B,
and C and then make the connections accordingly. The implementation of
this function using a 74152 IC is shown in Fig. Prob. 6.1(b). This IC also
has the data output which is complement of the data input line selected.
0
1
2
3
4
5
6
7
74152 Y
S2 S1 S0
D
D
Logic 1
Logic 0
A B C
Fig. Prob. 6.1(b)
6.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any
one of the following approaches.
(i) A 32:1 multiplexer will have five selection lines, say, A, B, C, D, and E,
where A is the MSB. If A is connected to the Enable input of one of the
16:1 multiplexers, while the enable input of the other multiplexer is
connected to A , then for A = 0, the first multiplexer is enabled and for
A = 1 the second multiplexer is enabled. Thus for the first 16 of the
32 data inputs one multiplexer gives output depending upon the select
inputs while for the remaining 16 data inputs the other multiplexer
gives the output. Now if the two outputs are ORed together, the system will
function as a 32:1 multiplexer. The complete circuit is shown in
Fig. Prob. 6.2(i).
(ii) Another method can use two 16:1 multiplexers with their select lines con-
nected together. This is followed by a 2:1 multiplexer to select one of the
two outputs. The select line of the 2 : 1 multiplexer is driven from input A.
The complete circuit is shown in Fig. Prob. 6.2(ii).
6.3 The truth table of a full-adder in given in Table Prob. 6.3. To realize this,
using 8:1 multiplexers requires one multiplexer for Sn and one for Cn output.
Assuming 74152 IC, the circuit is shown in Fig. Prob. 6.3.

67
S3 S2 S1 S0
Data
inputs
Output
F (A, B, C, D, E)
S3 S2 S1 S0
16
17
18
31
M2
Y2
Data
inputs
E
(LSB)
D
C
B
A
(MSB)
Fig. Prob. 6.2(i)
0
1
2
15
M1 Y1
16 : 1
16 : 1
0
1
2
15
Data
inputs M1 Y1
S3 S2 S1 S0
16
17
18
31
M2
Y2
S3 S2 S1 S0
Logic 0
B
C
D
E
(LSB)
Data
inputs
Logic 0
Output
Logic 0
F (A, B, C, D, E)
0
1
G3
A(MSB)
Fig. Prob. 6.2(ii)
16 : 1
2 : 1
M3 Y
16 : 1
S
·
ì
ïï
í
ï
ïî
ì
ïï
í
ï
ïî
ì
ïï
í
ï
ïî
ì
ï
ï
í
ï
ïî
G1
G1
G2
G2

68
Table Prob. 6.3
Inputs Outputs
An Bn Cn–1 Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The gates required for NAND-NAND realization are:
4-input NAND gate 1
3-input NAND gates 5
2-input NAND gates 3
Inverters 3
0
1
2
3
4
5
6
7
74152
IC1
Sn
S2 S1 S0
Logic 1
Logic 0
0
1
2
3
4
5
6
7
74152
IC2
Logic 1
Logic 0
S2 S1 S0
Cn
An
Bn
Cn–1
Fig. Prob. 6.3

69
Therefore, the following IC packages will be required:
7420 – 1
7410 – 2
7400 – 1
In contrast to four packages required in NAND-NAND realization, the real-
ization using 8:1 multiplexers require only 2 IC packages.
6.4 The A inputs are applied directly to the adder, whereas the B inputs are applied
through EX-OR gates. When the switch S is in ADD position the outputs of the
EX-OR gates will be same as the B inputs. Also Cin = 0. Therefore, the circuit
functions as a 4-bit adder. On the other hand, when S is in SUB position, the
EX-OR gates function as inverters. Also Cin = 1, therefore, the circuit adds A
to the 2’s complement of B and hence functions as a 4-bit subtractor. The
complete circuit is shown below.
7 4 8 3
4-bit Adder
B Input
B3 B2 B1 B0
6 744444 844444
A3 A2 A1 A0
Cin
ADD
SUB
VCC
S
6.5 Table Prob 6.5 (i) gives the truth table of Gray-to-BCD code converter.
Table Prob. 6.5(i)
Gray code BCD code
G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
C0 S3 S2 S1 S0
A input
6 74 84

70
(a) For A output
(i) When G3 G2 = 00 (ii) When G3G2 = 01
G1 G0 A G1 G0 A
0 0 0 1 0 0
0 1 1 1 1 1
1 1 0 0 1 0
1 0 1 0 0 1
A = G1 ⊕ G0 A = G1 ¤ G0
(iii) When G3 G2 = 10 (iv) When G3 G2 = 11
G1 G0 A G1 G0 A
1 0 X 0 0 0
1 1 X 0 1 1
0 1 X 1 1 X
0 0 X 1 0 X
A = X A = G1 ⊕ G0
Similarly, we can obtain the expressions for the D, C, and B outputs. These
are given in Table Prob. 6.5 (ii).
Table Prob. 6.5(ii)
G3 G2 D C B A
0 0 0 0 G1 G1 ⊕ G0
0 1 0 1 G1 G1 ¤ G0
1 0 X X X X
1 1 1 0 0 G1 ⊕ G0
The G3 and G2 are used as the select inputs. The complete circuit can be
drawn which requires two 74153 packages and one 7486 package.
(b) The complete circuit is shown in Fig. Prob. 6.5(b).
It requires one 74154, one 7430, one 7420, and one 7400 IC packages.
6.6 The truth table of BCD-to-7-segment decoder is given in Table Prob. 6.6(i)
and Fig. Prob 6.6(i) shows a common-anode 7-segment display device.
Table Prob. 6.6(i)
BCD Inputs Seven-Segment Outputs
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
(Contd.)

71
Table Prob. 6.6(i) (Contd.)
BCD Inputs Seven-Segment Outputs
D C B A a b c d e f g
0 1 1 0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 X X X X X X X
1 0 1 1 X X X X X X X
1 1 0 0 X X X X X X X
1 1 0 1 X X X X X X X
1 1 1 0 X X X X X X X
1 1 1 1 X X X X X X X
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
S3 S2 S1 S0
G3 G2 G1 G01 2444 3444
Gray code inputs
G1
G0
74154
(a) From Table Prob. 6.6(i), we can prepare Table Prob. 6.6(ii) which gives
outputs in terms of A and B inputs for each combination of D and C inputs.
The circuit for generating data inputs for the multiplexers corresponding to
Table Prob. 6.6 (ii) is shown in Fig. Prob. 6.6 (ii). The ICs required are:
74153 3 1
2
packages
Fig. Prob. 6.5(b)
BCD
outputs
A
(LSB)
B
C
D
(MSB)
ü
ï
ï
ï
ï
ï
ï
ï
ï
ï
ï
ïï
ý
ï
ï
ï
ï
ï
ï
ï
ï
ï
ï
ï
ïþ

72
B
A
A + B
AB
BÅA B¤A
B
BA
A
A + B
B A
(b) The circuit is designed in a way similar to Prob. 6.5. The ICs required are:
74154 one package
7420 one package
7410 one package
Fig. Prob. 6.6(ii)
7408 3/4 package
7432 3/4 package
7404 1/2 package
Table Prob. 6.6(ii)
Inputs Outputs
D C a b c d e f g
0 0 BA 0 BA BA A A + B B
0 1 A B ⊕ A 0 B ¤ A A + B AB AB
1 0 0 0 0 A A 0 0
1 1 X X X X X X X
a
b
c
d
e
f
g
Anode
a
f b
e c
g
d
DP
·
DP
Fig. Prob. 6.6(i)

73
7430 one package
7404 1/6 package
(c) The IC 7442 is a BCD-to-decimal decoder circuit with active-low outputs.
These outputs are to be connected exactly in the same way as in the case of
part (b) realization. The IC packages required are same as in part (b) with
74154 replaced by 7442.
(d) From the IC packages requirements for parts (a), (b), and (c), we observe
the savings in hardware when demultiplexers/decoders are used for the
realization of multiple output systems.
6.7 Table Prob. 6.5(i) can be rearranged suitably to give the truth table of BCD-to-
Gray code converter.
(a) From the truth table, Table Prob. 6.7 (a) is obtained following the
procedure used in Prob. 6.1(b).
Table Prob. 6.7(a)
D C B G3 G2 G1 G0
0 0 0 0 0 0 A
0 0 1 0 0 1 A
0 1 0 0 1 1 A
0 1 1 0 1 0 A
1 0 0 1 1 0 A
The circuit can now be designed using four 74151A ICs (one for each of
the outputs). The D, C, and B inputs are to be applied to the S2, S1, and S0
select inputs respectively.
(b) Table Prob. 6.7(b) can be obtained from the truth table following the
procedure of Prob. 6.5 (a). The circuit can now be designed using two
74153 ICs and two EX-OR (7486) gates.
Table Prob. 6.7(b)
D C G3 G2 G1 G0
0 0 0 0 B A ⊕ B
0 1 0 1 B A ⊕ B
1 0 1 1 0 A
1 1 X X X X
(c) Following the approach similar to (b), we obtain Table Prob. 6.7 (c). Here
eight rows of the truth table are grouped together.
Table Prob. 6.7(c)
D G3 G2 G1 G0
0 0 C B ⊕ C A ⊕ B
1 1 1 0 A

74
The circuit can now be designed using one 74157 (Quad 2:1 multiplexer)
IC and two EX-OR gates of 7486.
(d) Following the procedure used in Example 6.3, the circuit can be designed
using one BCD-to-decimal decoder IC 7442 and NAND gates (2-, 4-, 5-,
and 6-input).
(e) The minimized expressions are
G3 = D G2 = C + D G1 = CB + C B G0 = B A + B A
The realization will require eleven 2-input NAND gates.
(f) The package count for each part are given in Table Prob 6.7(d)
Table Prob. 6.7(d)
Part No. of IC packages
a 74151A – 4, 7404 – 1
b 74153 – 2, 7486 – 1
c 75157 – 1, 7486 – 1
d 7442 – 1, 7430 – 2, 7420 – 1
e 7400 – 3
6.8 The truth table for f1, f2, and f3 outputs is given in Table Prob. 6.8(i)
(a) The truth table is reduced to Table Prob. 6.8(ii) for realization using 8 : 1
multiplexers. The circuits can now be designed for f1, f2, and f3 outputs
using multiplexers and inverters.
(b) Using the truth table the circuits for f1, f2, and f3 can be designed following
the procedure outlined in Example 6.1. The realizations will require one 16
: 1 multiplexer for each output.
(c) The circuit can be designed using one demultiplexer and two 8-input and
one 6-input NAND gates.
Table Prob. 6.8(i)
Inputs Outputs
D C B A f1 f2 f3
0 0 0 0 1 1 0
0 0 0 1 0 1 0
0 0 1 0 0 1 1
0 0 1 1 1 1 0
0 1 0 0 0 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 0
1 0 0 0 0 0 1
1 0 0 1 1 0 0
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 1 1 1
1 1 0 1 0 0 0
1 1 1 0 0 1 0
1 1 1 1 1 1 0

75
Table Prob. 6.8(ii)
D C B f1 f2 f3
0 0 0 A 1 0
0 0 1 A 1 A
0 1 0 A 0 1
0 1 1 A 0 A
1 0 0 A 0 A
1 0 1 A A 0
1 1 0 A A A
1 1 1 A 1 0
6.9 In a 40:1 multiplexer, there are 40 data input lines (I0 through I39), 6 select
lines FEDCBA. The lower order three select bits C, B, and A are used as S2, S1,
S0 select inputs respectively for 8:1 multiplexers M1 through M5. The higher
order three select bits F, E, and D are used as select inputs S2, S1, and S0 for
the multiplexer M6, which selects output of one of the multiplexers M1 through
M5.
M1
S2 S1 S0
I0 – I7
I8 – I15
M3
S2 S1 S0
G
I16 – I23
I24 – I31
I32 – I39
S2 S1 S0
M2
G
Enable
S2 S1 S0
M5
G
M4
S2 S1 S0
G
0
1
2
3
4
5
6
7
G
Y
S2 S1 S0
F E D
M6
(MSB)
C B A
C B A
C B A (LSB)
Fig. Prob. 6.9
G

76
For example if the select inputs are 011111, data input 7 of M2 (I15) will
appear at the output Y.
6.10 The BCD-to-decimal decoder is to be used as an 1 : 8 demultiplexer. The
address inputs for demultiplexers D1 through D6 are C, B, and A. D is active-
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
D
C
B
A
7442
D1X2
X1
X0
(LSB)
8
9
10
11
12
13
14
15
D
C
B
A
7442
D2
16
17
18
19
20
21
22
23
7442
D3
24
25
26
27
28
29
30
31
D
C
B
A
7442
D4
32
33
34
35
36
37
38
39
D
C
B
A
7442
D5X2
X1
X0
X2
X1
X0
X2
X1
X0
(
X2
X1
X0
D
C
B
A
0
1
2
3
4
5
6
7
8
9
D6
7442
DEnable
X5 X4 X3
C B A
(MSB)
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Fig. Prob. 6.10

77
low input for demultiplexer function. The outputs 8 and 9 of D1 through D5 are
not used in this configuration. The lower order three bits of the address X2, X1,
and X0 are applied at the C, B, A select inputs respectively of each decoder
chip D1 through D5. The higher order three bits of the address X5, X4, and X3
are applied at the C, B, and A select inputs respectively of D6. For example, if
the 6-bit select inputs are 001111, then output 1 of D6 is activated, which
activates decoder D2 and the output 7 of this decoder goes low. This corre-
sponds to output on line 15 (which is same as the decimal equivalent of
001111). The complete circuit is shown in Fig. Prob. 6.10.
6.11 For the full-adder circuit designed using half-adder circuits shown in Fig.
Prob. 6.11.
Fig. Prob. 6.11
The propagation delay time for Cn is
tpd = tpd [EX-OR(1)] + tpd (AND-2) + tpd (OR) = 20 + 10 + 10 = 40 ns
This is the propagation delay time for carry to travel one full-adder. For an n-
bit adder, this carry has to ripple through all the n adders. Therefore, the
propagation delay time for the carry to propagate from C–1 to Cn–1 in the
circuit of Fig. 6.12 (a) will be n ´ 40 = 40 ns.
6.12 Let the four digits BCD numbers be P4P3P2P1 and Q4Q3Q2Q1. P4 and Q4 are
applied at the A and B inputs respectively of adder # 4 and similarly the other
inputs are applied as shown below.
Q4 P4 Q3 P3 Q2 P2 Q1 P1
C¢¢¢¢0 C2 C¢¢¢0 C1 C¢¢0 C0 C¢0 C–1
BCD adder BCD adder BCD adder BCD adder
#4 #3 #2 #1
C0 S15–S12 S11–S8 S7–S4 S3–S0
1 2444444444444444 3444444444444444
5-digit output
Fig. Prob. 6.12
EX–OR(1)
An
Bn
C1
S1
AND–1
EX–OR(2)
S2 = Sn
AND-2
OR
Cn–1
C2 Cn

78
6.13 Its truth table is given in Table Prob. 6.13. Using K-maps the minimized
expressions given below are obtained.
Table Prob. 6.13
Inputs Outputs
A1 A0 B1 B0 A > B A = B A < B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
A > B = A0 B 1 B0 + A1 A0 B 0 + A1 B 1
A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0)
= (A0 ¤ B0) (A1 ¤ B1)
A B, A = B,
and A B
A = B
A B
A > B
A = B
A B
A = B
A < B
Fig. Prob. 6.14
B0 – B3
A0 – A3
A4 – A7
B4 – B7

79
6.15 The operation is given below.
Inputs Outputs
CIC 1 A = 1001
B = 1011
A > B = 1 A > B = 0
A = B = 0 A B = 0
A > B = 1 A B = 0
A > B = 1 A B = 1
A > B = 1 A B = 0
A > B = 0 A B = 0
A > B = 0 A = B = 0
A = B = 0 A < B = 1
A < B = 1
6.16 The least-significant bit (A1) of BCD input is same as the least-significant bit
of the output. The other three bits (D1, C1, and B1) are applied to C, B, and A
inputs respectively. D and E inputs are connected to logic 0. The binary output
is obtained at B3B2B1B0 outputs as shown in Fig. Prob. 6.16.

80
74184
A1 B0
B1 B1
C1 B2
D1 B3
A Y1
B Y2
C Y3
D Y4
E Y5G
Binary
outputs
BCD
inputs
(MSB)
Fig. Prob. 6.16
ü
ïï
ý
ï
ïþ
ì
ïï
í
ï
ïî
6.17 The IC 74148 is a priority octal-to-binary encoder. If more than one inputs are
given in the same chip, the highest numbered input will appear in the binary
form at the output.
If two inputs are given simultaneously, one of which is in IC1 and the other
one in IC2, then E0 of IC2 will be HIGH, which will disable the IC1 chip. This
shows that the circuit is a priority encoder.
6.18 Apply the 6-bit input to A through F inputs and connect the other two inputs
G and H to logic 0. Connect EVEN and ODD inputs to logic 1 and 0 respec-
tively.
If the parity of the 6-bit word is even, å EVEN output will be 1, whereas, if
the parity of the 6-bit word is ODD, then å ODD output will be 1.
6.19 The 7-bit input is applied at A through G inputs and H = 0. If EVEN and ODD
inputs are at logic 1 and 0 respectively, then å EVEN output is 1 if the 7-bit
input is even and 0 if the 7-bit input is odd. Therefore, these seven bits along
with the å EVEN output bit will give an 8-bit word with odd parity. The
circuit is shown below.
A - G
8-bit odd
parity word
SEVEN
74180
SODD
A - G
H
EVEN
ODD
Logic 1 Logic 0
Fig. Prob. 6.19
ü
ï
ý
ïþ

81
6.20 The circuit is shown in Fig. Prob. 6.20 and its operation is given in Table
Prob. 6.20.
SEVEN
SODD
74180
Logic 1
Logic 0 G
H
P2
B14
B0 – B13
B8 – B13SEVEN
74180
P1
B0 – B7
SODD
EVEN
ODD
15-biteven
parityword
EVEN
ODD
Fig. Prob. 6.20
Table Prob. 6.20
Parity of B0 – B7 P1 Parity of P2
åEVEN åODD B8 – B13 åEVEN åODD
EVEN 1 0 EVEN 1 0
ODD 0 1
ODD 0 1 EVEN 0 1
ODD 1 0
From the table we see that the parity of B0 – B13 and åODD of P2 is
even.
6.21 The circuit is shown in Fig. Prob. 6.21 and its operation is explained in the
Table Prob. 6.21.
ü
ï
ý
ïþ
1 on
even parity
B0
B1
B2
B3
B4
B5
B6
B7
S EVEN
EVEN
SODD
ODD
74180
A
B
C
D
E
F
G
H
7486
Logic 1
B8
B9
Fig. Prob. 6.21

82
Table Prob. 6.21
Parity of Parity of Cascading Outputs
B0 – B7 B8 – B9 inputs
EVEN ODD åEVEN åODD
EVEN EVEN 1 0 1 0
EVEN ODD 0 1 0 1
ODD ODD 0 1 1 0
ODD EVEN 1 0 0 1
6.22
SEVEN
ODD
EVEN
P1
b0 – b7
b8
SEVEN
ODD
EVEN
P2
b9 – b16
b17
SEVEN
ODD
EVEN
P9
b72 – b79
b80
SEVEN
ODD
EVEN
P10
High on
EVEN
High on
ODD
Fig. Prob. 6.22
6.23 The circuit is given in Fig. Prob. 6.23. Here P1, P2, and P3 are 9-bit
parity checkers.
6.24 See Fig. Prob. 6.24 (a and b)
6.25 See Fig. Prob. 6.25
6.26 Let the four BCD digits be ABCD, with A as MSD. The circuit is given in
Fig. Prob. 6.26.
The least-significant bits of the BCD digits are applied at the data inputs of
M1 and similarly higher order bits are applied to M2, M3, and M4. The select
input are fed from the mod-4 counter, which drives a BCD-to-decimal
decoder.

83
SEVEN
SEVEN
SODD
SEVEN
P1
P2
P3
High on
EVEN
High on
ODD
Fig. Prob. 6.23
b0
b8
b9
b15
b16
b24
0
1
2
3
4
5
6
7
8
9
7442
VCC
GND
Current Limiting
resistor
D
C
B
A
(MSB)
BCDinput
VCC VCC
(a)
Fig. Prob. 6.24(a)
ì
ï
í
ï
î

84
+170 V
R = 10 kW Anode
NIXIE Tube
+5V VCC
74141
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9
D C B A
(LSB)
1 24444 34444
BCD Input
(b)
Fig. Prob. 6.24
(b)
A
B
C
D
Enable
(logic 0)
D1
0
1
2
3
15
E
F
G
H
Detects
0001
D2
0
1
14
15
Detects
0001111
Fig. Prob. 6.25
The multiplexer outputs are decoded by the BCD-to-7-segment decoder with
active-low outputs. When the counter output is 00, digit A is selected and at
the same time anode A1 goes HIGH, thereby displaying the digit A on the
left-most 7-segment display. Similarly, when the counter outputs are 01, 10,
and 11 B, C, and D digits are displayed respectively on second, third, and
fourth displays in sequence. In this way each display will be ON for one-
fourth of the total time. If the clock frequency is sufficiently high, the display
would appear to be continuous.
6.27 For R to glow, the inputs required at the rows for each column are as given in
Table Prob. 6.27.
The circuit is to be designed in a way similar to that of Prob. 6.26. One
column must glow at a time in sequence. Seven 5:1 multiplexers and a mod-5
counter will be required for this.

85
A0 0
B0 1
C0 2
D0 3
M1
S1 S0
A1 0
B1 1
C1 2
D1 3 S1 S0
A2 0
B2 1
C2 2
D2 3 S1 S0
M3
M2
A3 0
B3 1
C3 2
D3 3 S1 S0
M4
A
B
C
D
a
b
c
d
e
f
g A1 A2 A3 A4
Buffer
inverters
0 1 2 3 4
···
Q0 Q1 Q2 Q3
Mod-4 counter
Clock
Fig. Prob. 6.26
(MSB)
BCD-to-7-segment
decoder
BCD-to-decimal
decoder
Table Prob. 6.27
Row/Column ® 1 2 3 4 5
¯
1 1 1 1 1 0
2 1 0 0 0 1
3 1 0 0 0 1
4 1 1 1 1 0
5 1 0 1 0 0
6 1 0 0 1 0
7 1 0 0 0 1

86
CHAPTER 7
7.1 When S = R = 0, the outputs of the gates G3 and G4 will be 1. Therefore,
G1 and G2 will act as inverters. Hence, the circuit of fig. 7.4 is same as that of
Fig. 7.3.
7.2 (a) With S = 1 and R = 0, the outputs of G3 and G4 are 0 and 1 respectively.
Since one of the inputs of G1 is 0, therefore, its output Q = 1. This makes
both the inputs of G2 as 1 giving an output Q = 0. Now if S = R = 0, the
inputs and output of G2 remain unaffected, which makes the lower input of
G1 as 0 while the upper one becomes one giving again Q = 1. This means
the outputs do not change.
(b) With S = 0 and R = 1, Q1 = 1 and Q = 0 in a manner similar to part (a) and
also Q and Q will remain unchanged when S and R both are made 0.
7.3
S
R
Q
Q
Fig. Prob 7.3
7.4 (a) With Pr = 0, Q will be 0 which makes one of the inputs of G3 0. There-
fore, whatever may be the other input of G3, its output will be 1. This
results in both the inputs of AND gate G5 to be 1 giving Q = 1. That is, the
FLIP-FLOP is set irrespective of the S, R, and CK inputs.
(b) If Cr = 0, then the FLIP-FLOP is reset following the same logic as
discussed in part (a).
(c) If Pr = Cr = 1, the AND gates G5 and G6 are enabled, making this circuit
identical to a normal clocked S – R FLIP-FLOP as shown in Fig. 7.5.
7.5 (i) When Jn = Kn = 0, the AND gates are disabled resulting in Sn = Rn = 0.
Therefore, when a clock pulse is applied, the outputs Q and Q will not
change, i.e., Qn+1 = Qn.
(ii) When Jn = 1 and Kn = 0, then Sn = Q n and Rn = 0. Now, if Qn = 1 then
Sn = 0, i.e., Sn = Rn = 0 and the output Qn+1 = Qn = 1. On the other hand if
Qn = 0 then Sn = 1 which will make Qn+1 = 1. Therefore, whatever may be
the state of the FLIP-FLOP, it will go to set state in this condition when a
clock pulse is applied.
(iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn. Following the above
discussion, we find that the FLIP-FLOP will go to the reset state when a
clock pulse is applied.
(iv) If Jn = Kn = 1, then Sn = Q n and Rn = Qn. Now, if Qn = 1, then Sn = 0 and
Rn = 1 which will make Qn+1 = 0. Similarly, if Qn = 0, then Sn = 1 and Rn
= 0 which makes Qn+1 = 1. Therefore, Qn+1 = Q n.

87
7.6
Y1 = ⋅ ⋅( )J Q CK
= ⋅ ⋅J Q CK
and Y2 = ⋅ ⋅J Q CK
Hence, Y1 = Y2
7.7
Q1 = Q
and Q2 = Q
7.8
Clock
Input
Output
Clock
Input
Output
7.10
Clock
Input
Output
Q
7.11 Let Q = 1 and Q = 0.
This makes R = Q = 1 and S = Q = 0. When a clock pulse is applied, Q and
Q will become 0 and 1 respectively. Now, R = Q = 0 and S = Q = 1 and on
7.9
Q
Q
ì
í
î
Q
Q
ì
í
î

88
application of a clock pulse, Q and Q become 1 and 0 respectively. This
show that Q and Q change with every clock pulse, and hence the circuit
behaves as a toggle switch.
7.12 The truth table is given in Table Prob. 7.12. From this table we observe that
when Tn = 0, Qn+1 = Qn, whereas, when Tn = 1, Qn+1 = Q n.
Table Prob. 7.12
Tn Qn Sn Rn Qn+1
0 0 0 1 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 0
7.13 When Q = D = 0, a clock pulse will make Q and Q 0 and 1 respectively. Now
Q = D = 1 and the next clock pulse will change the Q output to 1. Thus, the
outputs change with every clock pulse.
7.14 The characteristic table and the truth table for decoder are given in Table
Prob. 7.14 (a). The K-maps for Y1 and Y2 are shown below, which give
Y1 = + + = ⋅ ⋅Q CK J Q J CK
and Y2 = + + = ⋅ ⋅CK K Q Q K CK
Table Prob. 7.14 (a)
Characteristic table Truth table for decoder
CK J K Qn Qn + 1 Y1 Y2
0 0 0 0 0 1 X
0 0 0 1 1 X 1
0 0 1 0 0 1 X
0 0 1 1 1 X 1
0 1 0 0 0 1 X
0 1 0 1 1 X 1
0 1 1 0 0 1 X
0 1 1 1 1 X 1
1 0 0 0 0 1 X
1 0 0 1 1 X 1
1 0 1 0 0 1 X
1 0 1 1 0 1 0
1 1 0 0 1 0 1
1 1 0 1 1 X 1
1 1 1 0 1 0 1
1 1 1 1 0 1 0
(b) The excitation table and the truth table for decoder are given in Table
Prob. 7.14(b). The K-maps can be prepared and minimized. The mini-
mized expressions are:

89
CKJ
KQ 00 01 11 10
´ ´ 1 ´
1 1 1 1
1 1 0 0
´ ´ 1 ´
CKJ
KQ00 01 11 10
1 1 0 1
´ ´ ´ ´
´ ´ 1 1
1 1 0 1
00
01
11
10
00
01
11
10
Y Q CK J
Q J CK
1 = + +
= ⋅ ⋅
(a)
Y CK K Q
Q K CK
2 = + +
= ⋅ ⋅
(b)
Y1 = + = ⋅CK D CK D
and Y = + = ⋅CK D CK D
Table Prob. 7.14(b)
Excitation table Truth table for decoder
CK D Qn Qn+1 Y1 Y2
0 0 0 0 1 X
0 0 1 1 X 1
0 1 0 0 1 X
0 1 1 1 X 1
1 0 0 0 1 X
1 0 1 0 1 0
1 1 0 1 0 1
1 1 1 1 X 1
(c) Using the above method, we obtain
Y1 = ⋅ ⋅CK T Q
and Y2 = ⋅ ⋅CK T Q
Complete circuits can be drawn for each of the above cases.
7.15 (a) The truth table required for conversion from S-R to D FLIP-FLOP is
given in Table Prob. 7.15(a). The K-maps for S and R outputs are prepared
as shown in Fig. Prob. 7.15(i) from which we obtain the minimized expres-
sions for S and R as
S = D and R = D
Table Prob. 7.15(a)
Data input Output S-R FF inputs
D Q S R
0 0 0 X
1 0 1 0
0 1 0 1
1 1 X 0

90
(b) The required truth table is given in Table Prob. 7.15(b) from which the
minimized expressions are obtained as
J = D and K = D
Table Prob. 7.15(b)
Data input Output J-K FF inputs
D Q J K
0 0 0 X
1 0 1 X
0 1 X 1
1 1 X 0
(c) The required truth table is given in Table Prob. 7.15(c) and the minimized
expression for D is given by
D = +JQ KQ
Table Prob. 7.15(c)
Data inputs Output D-FF input
J K Q D
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
1 0 1 1
(d) Table Prob. 7.15 (d) gives the required truth table from which we obtain
the minimized expressions for S and R as
S = ⋅T Q
and R = T ⋅ Q
D
Q 0 1
0 1
0 ´
0
1
D
Q 0 1
´ 0
1 0
0
1
(a) (b)
Fig. Prob. 7.15(i)

91
Table Prob. 7.15(d)
Data input Output S – R FF inputs
T Q S R
0 0 0 X
1 0 1 0
1 1 0 1
0 1 X 0
(e) The truth table can be prepared and expressions for J and K inputs
obtained.
J = K = T
Similarly, all the other conversions can be made. The minimized expres-
sions obtained are given below:
(f) T = J Q + KQ
(g) T = D ⊕ Q
(h) D = S + R Q
(i) D = T ⊕ Q
(j) T = SQ + RQ
(k) J = S, K = R
7.16 Let the inputs to the latch be Y1 and Y2.
(i) When the clock is LOW:
Y1 = Y2 = 1 independent of D input and the state of the FLIP-FLOP can-
not change.
(ii) When the clock is HIGH:
Y1 and Y2 are complement to each other and for each value of D we find
that the values of Y1 and Y2 do not change. This means the state of the
FLIP-FLOP cannot change.
(iii) When the clock goes from LOW to HIGH:
Case I: Let D = 0
Y1 will remain 1 and Y2 changes from 1 to 0. Therefore, Q becomes 0.
While the clock is HIGH, if there is any change in D, Y1 and Y2 will remain
unaltered. When the clock comes back to 0 from 1, then Y1 = Y2 = 1 which
also does not affect the output Q.
Case II: Let D = 1. Y2 will remain 1 and Y1 changes from 1 to 0. Therefore,
Q goes to 1.
Now, while the clock is HIGH, if there is any change in D, Y1 and Y2
will remain unaltered. When the clock goes back to 0, then Y1 = Y2 = 1
which will not affect the output Q.
7.17 The waveforms obtained are shown in Fig. Prob. 7.17.
7.18 (a) When the switch is in position 1, Pr = 0 and Cr = 1. Therefore, Q = 1.
Now, if the switch is changed over to position 0, as soon as it makes
contact for the first time, Q will become 0. Now, even if the switch

92
1
0
1
0
1
0
1
0
Clock
J
Q
Q
0 1 2 3 4 5 6 7 8 9 10 11 12
(a)
(b)
Fig. Prob. 7.17
debounces, the output Q will not be affected. Similarly, the switch will
operate in the reverse switching.
(b) When the switch is in position 1, Q = 0 and Q = 1. When the switch is
thrown to position 0, at the first contact Q becomes 1. Now, when the
switch debounces, the outputs Q and Q do not change.
7.19 The clock, CKs and CKD waveforms are shown in Fig. Prob. 7.19. At the rising
edge of the clock CKs, the data present at the data input terminal Ds is loaded
into the source FF. When CKD goes HIGH, the data is loaded into the destina-
tion FF.
Now, if the delay time Dt2 is more than it takes to change the present output
of the source FF, the operation will not be reliable. In fact, the clock skew may
violate the hold time requirements of the destination FF. This difficulty can be
overcome by adding additional delay to assure reliable operation.
Clock
CKS
CKD
Dt1
Dt2
Fig. Prob 7.19
7.20 The waveforms are shown in Fig. Prob. 7.20. The states of the counter are 00,
01 and 10.
7.21 The waveform at CK will be as shown in Fig. Prob. 7.21. This means, the level
triggered D-type FF will operate as a positive-edge-triggered FF.

93
1 2 3 4 5 6 7
1
0
1
0
1
0
1
0
Clock
pulses
J Q0 1=
Q0 = J1
Q1
Fig. Prob. 7.20
Fig. Prob. 7.21

94
CHAPTER 8
8.1 (i) When the mode control input, M = 1, all the A AND gates are enabled and
all the B AND gates are disabled. The circuit effectively reduces to that of
Fig. Prob. 8.1(i). This is a right-shift register.
D3 Q3 D2 Q2 D1 Q1 D0 Q0
FF3 FF2 FF1 FF0
Serial
input
(ii) When M = 0, all the B AND gates are enabled and all the A AND gates are
disabled. The circuit effectively reduces to that of Fig. Prob. 8.1(ii). In this
case the data will get shifted to the left direction, i.e., it functions as a left-
shift register.
Fig. Prob. 8.1(i)
Q3 D3 Q2 D2 Q1 D1 D0 Q0
FF3 FF2 FF1 FF0
Serial
input
Fig. Prob. 8.1(ii)
8.2 A 5-stage twisted-ring counter is shown in Fig. Prob. 8.2(a). Let us assume
that all the FLIP-FLOPs are in the clear state, i.e., Q4 = Q3 = Q2 = Q1 = Q0 =
0. The various outputs when clock pulses are applied are given in Table Prob.
8.2.
Table Prob. 8.2
At the end of Outputs
clock pulse Q4 Q3 Q2 Q1 Q0
0 0 0 0 0 0
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 0
5 1 1 1 1 1
6 0 1 1 1 1
7 0 0 1 1 1
8 0 0 0 1 1
9 0 0 0 0 1
10 0 0 0 0 0
At the end of the tenth clock pulse, the circuit comes back to its initial state.
Therefore, it is a mod-10 counter. Its state diagram is shown in Fig. Prob. 8.2(b).

95
8.3 Let Y0, Y1. . . be the outputs corresponding to pulses 0, 1, 2, . . . respectively.
The truth table for the decoder is given in Table Prob. 8.3. For all the remain-
ing combinations of Q’s, the Y outputs are don’t care. The K-map is to be
prepared for each output. Figure Prob. 8.3 gives the K-map for Y0 . Similarly,
other K-maps can be prepared. The minimized expressions are given by
Y0 = Q Q4 0 Y5 = Q4Q0
Y1 = Q4Q 3 Y6 = Q 4Q3
Y2 = Q3Q 2 Y7 = Q 3Q2
Y3 = Q2Q 1 Y8 = Q 2Q1
Y4 = Q1Q 0 Y9 = Q 1Q0
Table Prob. 8.3
Inputs Outputs
Q4 Q3 Q2 Q1 Q0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 1 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 1 0 0 0 0
0 1 1 1 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0
0 0 0 1 1 0 0 0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
D4 Q4 D3 Q3 D2 Q2 D1 Q1 D0 Q0
Clock
Clear
FF4 FF3 FF2 FF1 FF0
Q0
Fig. Prob. 8.2(a)
00000 10000 11000 11100 11110
00001 00011 00111 01111 11111
Fig. Prob. 8.2(b)

96
00 01 11 10
1 ´ ´ ´
0 ´ ´ ´
0 0 0 ´
´ ´ ´ ´
Q3Q2
Q1Q0
00
01
11
10
00 01 11 10
0 ´ 0 0
´ ´ ´ ´
´ ´ 0 ´
´ ´ 0 ´
Q3Q2
Q1Q0
00
01
11
10
Q4 = 0 Q4 = 1
Fig. Prob. 8.3
8.4 To generate these waveforms, a 4-stage twisted-ring counter is required. The
waveforms at the Q outputs are shown in Fig. Prob. 8.4(i). The required,
waveforms can be obtained by using decoders shown in Fig. Prob. 8.4(ii),
which are designed in the same way as Prob. 8.3.
The circuit can be drawn using ten 2-input AND gates.
1 2 3 4 5 6 7 8 9 10 11 12 13
Clock
Pulses
Q3
Q2
Q1
Q0
Fig. Prob. 8.4(i)
Q3
Q2
Q1
Q0
f1 f2
Q2 Q0
f3 f4
Q3 Q1
Fig. Prob. 8.4(ii)
8.5 The count sequence is given in Table Prob. 8.5. From the count sequence we
observe that Q0 changes with every clock pulse. This can be obtained by using
a T-type FLIP-FLOP (FF0) with T0 = 1.

97
T0 = T1 = T2 = 1
T0
Clock
Q0
Q0
T1
FF1
Q1
T2
FF2
Q2
Q1 Q2
Q1 changes whenever Q0 changes from 0 to 1, therefore, if Q0 is used as the
clock input for FF1 with T1 = 1, the desired changes in Q1 will be obtained.
Similarly, Q2 changes whenever Q1 goes from 0 to 1. The desired changes in
Q2 can be obtained by using Q1 as the clock input for FF2 with T2 = 1. The
complete circuit is shown in Fig. Prob. 8.5.
FF0
Fig. Prob. 8.5
Table Prob. 8.5
Q2 Q1 Q0
0 0 0
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
8.6 For a ripple UP counter Q outputs of the preceding stages are to be connected
to the clock inputs of the succeeding stages, whereas for a DOWN counter Q
outputs are to be connected to the clock inputs. Therefore, AND-OR gates are
used between stages as shown below. The AND gates A are enabled when UP/
DOWN input is at logic 1, connecting Q outputs to clock inputs, whereas the
AND gates B are enabled when UP/DOWN input is at logic 0 connecting Q
outputs to the clock inputs.
T0 T1 T2 T3
FF0 FF1 FF2 FF3
A0
A1 A2
Q1 Q2 Q3
Q0
T0 = T1 = T2 = T3 = 1
Q0 Q1 Q2 Q3B0
B1 B2
UP/
DOWN
Clockpulses
Fig. Prob. 8.6

98
D0 D1 D2 D3
Load
Q0 Q1
Q2
Q3
FF3FF2FF1FF0
Q0 Q1 Q2
Q3
PrPr PrPr
Fig. Prob. 8.7
The preset inputs are used for asynchronous loading. The relevant portion of
the circuit is shown on next page. When load input is HIGH, the data at the D
inputs will be entered in the FLIP-FLOPs. The other details will be same as
in Prob. 8.6.
8.8 At the end of the tenth pulse Q3 = Q1 = 1, the output of G becomes 0. Also
CK = 0, therefore, the output of the latch is 0. Now if Q1 or Q3 goes to 0, the
output of the latch continues to be 0.
When the eleventh clock pulse appears at CK, the output of the latch will go
to 1 and normal counting will proceed.
8.9 (a) For the divide-by-5 circuit, the count sequence will be 000, 001, 010, 011,
100, 000. Therefore, as soon as the count reaches 101, all the three FLIP-
FLOPs must be cleared. The circuit is shown in Fig. Prob. 8.9.
T0 = T1 = T2 = 1
T0
T1
Clock
pulses
FF0
Q0
FF1
Q1
Q1
T2 Q2
FF2
Q2
Q0Cr
Cr Cr
Fig. Prob. 8.9
(b) For the divide-by-7, the resetting of FLIP-FLOPs is required as soon as
the count reaches 111. Therefore, a 3-input NAND gate with inputs Q0, Q1,
and Q2 will be required to clear the FLIP-FLOPs.
8.10 The waveforms are shown in Fig. Prob. 8.10. It is clear from the waveforms
that the frequency divisions by 3, 6, and 12 are obtained at the QC, QD, and QA
outputs respectively.

99
Output
QA
QB QC
QD
A input
B inputClock
pulses
7 4 9 2
R1
R2
Fig. Prob. 8.11(a)
1 2 3 4 5 6 7 8 9 10 11 12 13
1
0
1
0
1
0
1
0
1
0
Clock
pulses
QD
QC
QB
QA
Fig. Prob. 8.10
8.11 The states of the circuit of Prob. 8.10 are given below.
QD QC QB QA
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
1 0 1 0
1 1 0 0
0 0 0 1
0 0 1 1
0 1 0 1
1 0 0 1
1 0 1 1
1 1 0 1
0 0 0 0
(a) The ÷ 7 counter is obtained by terminating the count sequence when
QB = QA = 1. The circuit is shown in Fig. Prob. 8.11(a).

100
(b) The ÷ 9 counter is obtained by terminating the count sequence as soon as
QD = QA = 1. The circuit is shown in Fig. Prob. 8.11(b).
8.12 If we use the complements of QD, QC, QB, and QA as outputs, we obtain the
DOWN counter. The sequence is given in Table Prob. 8.12.
QD QC QB QA
0 0 0 0
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
Output
7 4 9 2
QDQCQB
QA
A input
B input
Clock
pulses R1
R2
Fig. Prob. 8.11(b)
(c) The ÷ 11 counter is obtained by terminating the count sequence as soon as
QD = QC = QA = 1. The circuit is shown in Fig. Prob. 8.11(c).
QA QDQCQB
A input
B input
Clock
pulses
7 4 9 2
R1
R2
Output
·
Fig. Prob. 8.11(c)
(Contd.)

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