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Developing
Software for
Persistent
Memory
Thomas Willhalm
Intel Deutschland
GmbH
DisclaimerBy using this document, in addition to any agreements you have with Intel, you accept the terms set forth below.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR
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PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change
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published specifications. Current characterized errata are available on request.
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Do not finalize a design with this information.
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Copyright © 2015 Intel Corporation. All rights reserved
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2
Intel 3D XPoint
Technology
https://youtu.be/OaAjLyPtoyE
1000Xfaster
THAN NAND
1000Xendurance
OF NAND
10Xdenser
THAN CONVENTIONAL
MEMORY
Agenda
• Technology Differentiators
– Benefits and caveats to persisting data
structures
– Why programming to persistent memory is
different
• Case study: Design of a Persistent Memory
Enabled Database
– Design decisions
– Experimental evaluation
Technology
Differentiators
Differentiators for Persistent Memory Technologies
Large
capacity
Higher density will allow larger DIMMs
Persistence Data stored in PMem will remain in
memory after reboot
Higher
latencies
Latencies higher than DRAM (100ns) but
much less than latest gen-PCIe SSDs
(10,000 ns)
What value do these technology differentiators offer?
Opportunity: Persistence
in Memory Tier
Memory meeting disk is a potential game changer for applications!
Working store of data
For decades of computing…
Byte addressable
Low latency
High bandwidth
Persistent
Very Large Capacity
!= Durable store of data
Load from disk
Wait for disk IO
Now: Persistent Memory
One store to rule them all!
Byte addressable
Low latency
High bandwidth
Persistent
Large capacity
Opportunity:
Large Capacity
• Larger datasets in memory:
– Less paging, improved performance
• Scale-up vs. scale-out for in-memory solutions
– Fewer hosts with iso-memory size
Large capacity: avoid disk accesses, benefit in-memory
Opportunity:
Fast restart
Minimize restart time to improve data
availability
Availability
Annual
DownTime
97% 11 days
98% 7 days
99% 3 days 15 hrs
99.9% 8 hrs 48 min
99.99% 53 min
99.999% 5 min
99.9999% 32 sec
• Loading TBs of data
in memory can take
minutes or hours
• Millions of dollars lost
per hour due to
downtime**
**http://tanejagroup.com/files/Compellent_TG_Opinion_5_Nines_Sept_20121.pdf
Caveat:
Higher Memory Latencies
• Why not hold all data in PMem: higher latencies
• What are considerations for moving a data
structure to PMem?
Data Layout and
Size
• Can caching hide
latency for data
layout/size?
• Example: Arrays vs.
linked lists
Frequency of
Access
• Are data references
frequent &
performance-critical?
• Example: cold vs.
hot stores
Access Pattern
• Are data access
patterns prefetch &
cache friendly?
• Example: hash
lookups vs column
scans
Need to identify application performance sensitivity for persisted
data structures
Data Structure Latency
Sensitivity
Workloads with sequential
memory access patterns perform
well on PMem
DRAM PMem DRAM PMem DRAM PMem
prefetch no-prefetch prefetch
Scan B+-Tree
Workloads with random memory
access patterns do not perform
well on PMem.; prefer DRAM
“Scan” and “B+-Tree” performance on
DRAM and PMem
-7% -37%
Prefetching can
hide latency
for “scan”
Prefetching
cannot hide
latency
for “B+-Tree”
Software Architecture:
Persistent Memory
Benefit from larger
memory capacity?
Benefit from
persistence?
Latency tolerance
Persistent
Memory
Identify latency, bandwidth
sensitive data-structures
Identify data-
structures for PMem
Prototype application
for PM/DRAM layout
Quantify performance
impact
Quantify value
proposition
Decide if the tradeoff
is acceptable
Persistent
Memory
yes
high
low
yes
no
no
yes
DRAM
no
Systematically identify which data structures can benefit from
Persistent Memory
Persistent Memory
Aware File Systems
• No buffering in DRAM on mmap  direct access to PMem
• EXT4 and XFS + new "dax" mount (4.0 kernel onward)
– PMFS (research)
Map Persistent Memory in address space with “mmap”
NVM DIMM
User
Space
Kernel
Space PMem Block Driver
File System
Application
Block File Memory
Load,
Store
Standard
File API
PMem-
aware FS
MMU
Mappings
Cache Line
Block
fopen(.. )
mmap(.. )
Persisting Data on the Fly
New instructions CLFLUSHOPT and PCOMMIT required to make
stores durable
Cache PMem
var 1 1
persisted True True
Int var = 0;
Bool persisted = false;
…
var = 1;
MFENCE;
Flush var;
MFENCE;
persisted = true;
MFENCE;
Flush persisted;
MFENCE;
PCOMMIT;
MFENCE;
…
Cache PMem
var 1 0
persisted True True
Cache PMem
var 0 0
persisted False False
Before
After (incorrect)
After (correct)
Not flushed
Flushing Caches
Instruction Meaning
CLFLUSH addr
Cache Line Flush:
Available for a long time
CLFLUSHOPT addr
Optimized Cache Line Flush:
New to allow concurrency
CLWB addr
Cache Line Write Back:
Leave value in cache for performance of next
access
Flushing Memory Controller
Mechanism Meaning
PCOMMIT
Persistent Commit:
Flush stores accepted by memory subsystem
Asynchronous DRAM
Refresh
Flush outstanding writes on power failure
Platform-Specific Feature
PMEM.IO
• Open source persistent memory libraries
• https://pmem.io/
• Example: libpmemobj provides transactional object store
• providing memory allocation, transactions, and general facilities
for persistent memory programming.
Website discusses library functions, caveats, suggestions on
programming to PMem
Agenda
• Technology Differentiators
– Benefits and caveats to persisting data
structures
– Why programming to persistent memory is
different
• Case study: Design of a Persistent Memory
Enabled Database
– Design decisions
– Experimental evaluation
Instant Recovery for Main-Memory Databases
Ismail Oukid*°, Wolfgang Lehner*, Thomas Kissinger*, Peter Bumbulis°,
and Thomas Willhalm
+
*TU Dresden °SAP SE
+Intel GmbH
CIDR 2015, California, USA,
January 5, 2015
Design Considerations
Eliminate data
copy from storage
• Directly modify data
in persistent memory
Eliminate log
infrastructure
• Use concurrent and
persistent data
structures
• combined with
concurrency scheme
Dynamic
placement of
secondary data
structures
• Use performance
considerations to
place secondary data
structures in DRAM
or PMem (SCM)
Three main design considerations for instant and point-in-time
recovery
Take full advantage of persistent memory
SOFORT: A PMem-
enabled architecture
SOFORT is a single-level column-store.
The working copy is the durable copy
Log
log
buffer
buffer pool
… …
runtime data
Traditional Architecture
Database
database
runtimedata
PMem-enabled Architecture
HDD DRAM PMem
Log
Transient
Main
Memory
Persistent
Storage
Transient
Main
Memory
Non-Volatile
Main
Memory
Moving the
persistency
bar
Database
Simulating Memory
Latency
Hardware-based PMem simulation based on DRAM:
• Special BIOS, tunable DRAM latency with means of a
microcode patch
• Limitation: symmetric instead of asymmetric read/write
latency
• Avoiding NUMA effects: benchmark run on a single socket
• DRAM Latency: 90ns, simulated PMem latency: 200ns
Evaluation: Recovery Time
Throughput: -0%
Recovery area: -16%
Recovery delta: ~8s
Synchronous
Recovery
Instant Recovery
0% indexes in PMem 40% indexes in PMem 100% indexes in PMem
First query accepted
after ~8s,
Recovery delta = 8s
Throughput: -14%
Recovery area: -82%
Recovery delta: <2s
Throughput: -30%
Recovery area: -99,8%
Recovery delta: <5ms
Different type of tradeoffs possible between throughput and
recovery metrics
Evaluation: Throughput
Vs. Recovery
23
Curves are not linear:
secondary data structures
are not equally important for
TATP benchmark
Throughput drop limited to
30%
Taking advantage of a workload’s characteristics leads to an
optimal tradeoff
Summary
• Persistent Memory offers the game-changing ability to
improve restart and recovery time, and improve
capacity
• Design process involves deciding which data structures
to persist
• Moving a data structure to PMem avoids the need to
load from disk on restart altogether
• Tools, Libraries, Test platforms available

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Developing Software for Persistent Memory / Willhalm Thomas (Intel)

  • 2. DisclaimerBy using this document, in addition to any agreements you have with Intel, you accept the terms set forth below. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Results have been estimated based on internal Intel analysis and are provided for informational purposes only. Any difference in system hardware or software design or configuration may affect actual performance. Intel, the Intel logo, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries. Copyright © 2015 Intel Corporation. All rights reserved *Other brands and names may be claimed as the property of others. 2
  • 5. Agenda • Technology Differentiators – Benefits and caveats to persisting data structures – Why programming to persistent memory is different • Case study: Design of a Persistent Memory Enabled Database – Design decisions – Experimental evaluation
  • 6. Technology Differentiators Differentiators for Persistent Memory Technologies Large capacity Higher density will allow larger DIMMs Persistence Data stored in PMem will remain in memory after reboot Higher latencies Latencies higher than DRAM (100ns) but much less than latest gen-PCIe SSDs (10,000 ns) What value do these technology differentiators offer?
  • 7. Opportunity: Persistence in Memory Tier Memory meeting disk is a potential game changer for applications! Working store of data For decades of computing… Byte addressable Low latency High bandwidth Persistent Very Large Capacity != Durable store of data Load from disk Wait for disk IO Now: Persistent Memory One store to rule them all! Byte addressable Low latency High bandwidth Persistent Large capacity
  • 8. Opportunity: Large Capacity • Larger datasets in memory: – Less paging, improved performance • Scale-up vs. scale-out for in-memory solutions – Fewer hosts with iso-memory size Large capacity: avoid disk accesses, benefit in-memory
  • 9. Opportunity: Fast restart Minimize restart time to improve data availability Availability Annual DownTime 97% 11 days 98% 7 days 99% 3 days 15 hrs 99.9% 8 hrs 48 min 99.99% 53 min 99.999% 5 min 99.9999% 32 sec • Loading TBs of data in memory can take minutes or hours • Millions of dollars lost per hour due to downtime** **http://tanejagroup.com/files/Compellent_TG_Opinion_5_Nines_Sept_20121.pdf
  • 10. Caveat: Higher Memory Latencies • Why not hold all data in PMem: higher latencies • What are considerations for moving a data structure to PMem? Data Layout and Size • Can caching hide latency for data layout/size? • Example: Arrays vs. linked lists Frequency of Access • Are data references frequent & performance-critical? • Example: cold vs. hot stores Access Pattern • Are data access patterns prefetch & cache friendly? • Example: hash lookups vs column scans Need to identify application performance sensitivity for persisted data structures
  • 11. Data Structure Latency Sensitivity Workloads with sequential memory access patterns perform well on PMem DRAM PMem DRAM PMem DRAM PMem prefetch no-prefetch prefetch Scan B+-Tree Workloads with random memory access patterns do not perform well on PMem.; prefer DRAM “Scan” and “B+-Tree” performance on DRAM and PMem -7% -37% Prefetching can hide latency for “scan” Prefetching cannot hide latency for “B+-Tree”
  • 12. Software Architecture: Persistent Memory Benefit from larger memory capacity? Benefit from persistence? Latency tolerance Persistent Memory Identify latency, bandwidth sensitive data-structures Identify data- structures for PMem Prototype application for PM/DRAM layout Quantify performance impact Quantify value proposition Decide if the tradeoff is acceptable Persistent Memory yes high low yes no no yes DRAM no Systematically identify which data structures can benefit from Persistent Memory
  • 13. Persistent Memory Aware File Systems • No buffering in DRAM on mmap  direct access to PMem • EXT4 and XFS + new "dax" mount (4.0 kernel onward) – PMFS (research) Map Persistent Memory in address space with “mmap” NVM DIMM User Space Kernel Space PMem Block Driver File System Application Block File Memory Load, Store Standard File API PMem- aware FS MMU Mappings Cache Line Block fopen(.. ) mmap(.. )
  • 14. Persisting Data on the Fly New instructions CLFLUSHOPT and PCOMMIT required to make stores durable Cache PMem var 1 1 persisted True True Int var = 0; Bool persisted = false; … var = 1; MFENCE; Flush var; MFENCE; persisted = true; MFENCE; Flush persisted; MFENCE; PCOMMIT; MFENCE; … Cache PMem var 1 0 persisted True True Cache PMem var 0 0 persisted False False Before After (incorrect) After (correct) Not flushed
  • 15. Flushing Caches Instruction Meaning CLFLUSH addr Cache Line Flush: Available for a long time CLFLUSHOPT addr Optimized Cache Line Flush: New to allow concurrency CLWB addr Cache Line Write Back: Leave value in cache for performance of next access Flushing Memory Controller Mechanism Meaning PCOMMIT Persistent Commit: Flush stores accepted by memory subsystem Asynchronous DRAM Refresh Flush outstanding writes on power failure Platform-Specific Feature
  • 16. PMEM.IO • Open source persistent memory libraries • https://pmem.io/ • Example: libpmemobj provides transactional object store • providing memory allocation, transactions, and general facilities for persistent memory programming. Website discusses library functions, caveats, suggestions on programming to PMem
  • 17. Agenda • Technology Differentiators – Benefits and caveats to persisting data structures – Why programming to persistent memory is different • Case study: Design of a Persistent Memory Enabled Database – Design decisions – Experimental evaluation
  • 18. Instant Recovery for Main-Memory Databases Ismail Oukid*°, Wolfgang Lehner*, Thomas Kissinger*, Peter Bumbulis°, and Thomas Willhalm + *TU Dresden °SAP SE +Intel GmbH CIDR 2015, California, USA, January 5, 2015
  • 19. Design Considerations Eliminate data copy from storage • Directly modify data in persistent memory Eliminate log infrastructure • Use concurrent and persistent data structures • combined with concurrency scheme Dynamic placement of secondary data structures • Use performance considerations to place secondary data structures in DRAM or PMem (SCM) Three main design considerations for instant and point-in-time recovery Take full advantage of persistent memory
  • 20. SOFORT: A PMem- enabled architecture SOFORT is a single-level column-store. The working copy is the durable copy Log log buffer buffer pool … … runtime data Traditional Architecture Database database runtimedata PMem-enabled Architecture HDD DRAM PMem Log Transient Main Memory Persistent Storage Transient Main Memory Non-Volatile Main Memory Moving the persistency bar Database
  • 21. Simulating Memory Latency Hardware-based PMem simulation based on DRAM: • Special BIOS, tunable DRAM latency with means of a microcode patch • Limitation: symmetric instead of asymmetric read/write latency • Avoiding NUMA effects: benchmark run on a single socket • DRAM Latency: 90ns, simulated PMem latency: 200ns
  • 22. Evaluation: Recovery Time Throughput: -0% Recovery area: -16% Recovery delta: ~8s Synchronous Recovery Instant Recovery 0% indexes in PMem 40% indexes in PMem 100% indexes in PMem First query accepted after ~8s, Recovery delta = 8s Throughput: -14% Recovery area: -82% Recovery delta: <2s Throughput: -30% Recovery area: -99,8% Recovery delta: <5ms Different type of tradeoffs possible between throughput and recovery metrics
  • 23. Evaluation: Throughput Vs. Recovery 23 Curves are not linear: secondary data structures are not equally important for TATP benchmark Throughput drop limited to 30% Taking advantage of a workload’s characteristics leads to an optimal tradeoff
  • 24. Summary • Persistent Memory offers the game-changing ability to improve restart and recovery time, and improve capacity • Design process involves deciding which data structures to persist • Moving a data structure to PMem avoids the need to load from disk on restart altogether • Tools, Libraries, Test platforms available