Introduction to ARM
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Introduction to ARM
- 1. ARM Advanced RISC Machine Kelompok 1 IF5130 – Sistem Komputer
- 2. Are you using this ? Windows Phone
- 3. great performance , GREAT (computing) power
- 4. Low computing power, great performance
- 5. History Developed in 1985 at Acorn Computers Ltd for the 1st time Established a new company named Advanced RISC Machine Continuation of the architecture enchancements from the original architecture
- 6. ARM features A large register file A load/store architecture Uniform and fixed length instruction field Simple addressing mode
- 7. Data Sizes & Instruction Sets A 32-bit architecture Byte,halfword,Word relation to ARM Implement 32-bit ARM IS 16-bit Thumb IS Jazell to execute Java bytecode
- 8. Processor Mode User FIQ IRQ Supervisor Abort Undef System
- 9. New features Control over both ALU & shifter Auto-increment & decrement Load / Store Multiple Instructions Conditional execution
- 10. More Control Windows Phone
- 11. Data Processing – Dataflow Model
- 12. Data Processing – Component
- 13. Data Processing - Instructions Contains: • Arithmetic instructions • Comparisons instructions (no results - just set condition codes) Multipy Instructions • Logical operations • Data movement between registers
- 14. Data Processing – Instruction
- 15. Data Processing – LSL Example
- 16. Data processing ARM != pure RISC
- 17. Load & Store Instruction
- 19. Load/Store Instruction (2) 3 type transfer Single register data transfer (LDR/STR) Block data transfer (LDM/STM) Single Data Swap (SWP)
- 21. r0 Source Memory 0x5 Register Offset for STR 12 0x20c 0x5 r1 Base 0x200 0x200 Register Memory Updated r1 Offset r0 Source Base 0x20c 12 0x20c 0x5 Register Register for STR 0x200 0x5 r1 Original Base 0x200 Register
- 23. Stack
- 24. Block Data Transfer • Block Copying Modes Increment – After Increment – Before r13 Decrement – After r14 Increasing Memory Decrement – Before r12 loop LDMIA r12!, {r0-r11} ; load 48 bytes STMIA r13!, {r0-r11} ; and store them CMP r12, r14 ; check for the end BNE loop ; and loop until done
- 25. Conditional Execution Windows Phone
- 27. Conditional Execution Conditional flags N : Negative Z : Zero C : Carry V : Overflow
- 28. Conditional Execution Who’s reading flags? EQ : Equal HI : Higher NE : Not equal LS : Lower than or same VS : Overflow set GE : Greater than or equal VC : Overflow clear LT : Less than MI : Minus GT : Greater than PL : Plus LE : Less than or equal CS : Carry set CC : Carry clear
- 29. Conditional Execution C programing language While (i != j) { if (i > j) { i -= j; } else { j -= i; } }
- 30. Conditional Execution RISC loop: CMP Ri, Rj BEQ done BGT bigger BLT smaller bigger: SUB Ri, Ri, Rj BNE loop smaller: SUB Rj, Rj, Ri BNE loop
- 31. Conditional Execution ARM loop: CMP Ri, Rj SUBGT Ri, Ri, Rj SUBLT Rj, Rj, Ri BNE loop
- 32. Let’s recap Windows Phone
- 33. Reference [ZHU09 ]Dr Yifeng Zhu, The ARM Assembly, 2009, (http://arch.eece.maine.edu/ece471/images/8/8b/Lecture_05_ ARM_ISA.pdf) [ARM11] ARM Ltd., ARM Architecture Reference Manual, 2011, www.arm.com [ROK11] Rokov, Josko , ARM Architecture and Multimedia Applications (http://www.fer.unizg.hr/_download/repository/Kvalifikacijski- Rokov.pdf)
- 34. Reference The ARM Instructions Set – ARM University Program v1.0 [ARM11] ARM Ltd., ARM Architecture Reference Manual, 2011, www.arm.com www.ida.liu.se/~TDTS51/lectures/lectures5-6.pdf ARM7-TDMI-manual-pt2
- 35. ARM Advanced RISC Machine Kelompok 1 IF5130 – Sistem Komputer
Notas do Editor
- After achieving success with the BBC Micro computer, Acorn Computers Ltd considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that would soon be dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required a number of second processors to be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were unsuitable, and the 6502 was not powerful enough for a graphics based user interface.[citation needed]Acorn would need a new architecture, having tested all of the available processors and found them wanting. Acorn then seriously considered designing its own processor, and their engineers came across papers on the Berkeley RISC project. They felt it showed that if a class of graduate students could create a competitive 32-bit processor, then Acorn would have no problem. A trip to the Western Design Center in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers Steve Furber[5] and Sophie Wilson that they did not need massive resources and state-of-the-art R&D facilities.Wilson set about developing the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Micro with a second 6502 processor. It convinced the Acorn engineers that they were on the right track. Before they could go any further, however, they would need more resources. It was time for Wilson to approach Acorn's CEO, Hermann Hauser, and explain what was afoot. Once the go-ahead had been given, a small team was put together to implement Wilson's model in hardware.
- The cause of confusion here is the term “word” which will mean 16-bits to people with a 16-bit background.In the ARM world 16-bits is a “halfword” as the architecture is a 32-bit one, whereas “word” means 32-bits.Java bytecodes are 8-bit instructions designed to be architecture independent. Jazelle transparently executes most bytecodes in hardware and some in highly optimized ARM code. This is due to a tradeoff between hardware complexity (power consumption & silicon area) and speed.60 % bytecode di hardware
- The ARM has seven basic operating modes:User : unprivileged mode under which most tasks runFIQ : entered when a high priority (fast) interrupt is raisedIRQ : entered when a low priority (normal) interrupt is raisedSupervisor : entered on reset and when a Software Interrupt instruction is executedAbort : used to handle memory access violationsUndef : used to handle undefined instructionsSystem : privileged mode using the same registers as user modeThe Programmers Model can be split into two elements - first of all, the processor modes and secondly, the processor registers. So let’s start by looking at the modes.Now the typical application will run in an unprivileged mode know as “User” mode, whereas the various exception types will be dealt with in one of the privileged modes : Fast Interrupt, Supervisor, Abort, Normal Interrupt and Undefined (and we will look at what causes each of the exceptions later on).NB - spell out the word FIQ, otherwise you are saying something rude in German!One question here is what is the difference between the privileged and unprivileged modes? Well in reality very little really - the ARM core has an output signal (nTRANS on ARM7TDMI, InTRANS, DnTRANS on 9, or encoded as part of HPROT or BPROT in AMBA) which indicates whether the current mode is privileged or unprivileged, and this can be used, for instance, by a memory controller to only allow IO access in a privileged mode. In addition some operations are only permitted in a privileged mode, such as directly changing the mode and enabling of interrupts.All current ARM cores implement system mode (added in architecture v4). This is simply a privileged version of user mode. Important for re-entrant exceptions because no exceptions can cause system mode to be entered.
- Prosesnya :1. Data basukmelaluiData bus2. Data dapatmerupakanInstruction yang harusdieksekusiatauData Item3. Instruction decoder mentranslasiinstruksisebelumdieksekusi4. Load instructions copy data dari memory ke register dansebaliknya instructions copy data from register ke memory (gaada data processing instructions 5. yang secaralangsungmemanipulasi data dalam memory6. Data Item ditempatkandiregister file. Dua register sumberadalah (RndanRm), dan single result register Rd. Rmbisadi preprocessed dalam barrel shifter sebelummasukke ALU.7. Bersamasama barrel shifter dan ALU bisamengkalkulasikanekspresidanpengalamatannya.8. Setelahmelewati ALU, hasilnyadituliskedalam Rd dandikembalikanke register menggunakanResult bus.
- The Barrel ShifterA barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle* The ARM doesn’t have actual shift instructions.* Instead it has a barrel shifter which provides a mechanism to carry out shifts as part of other instructions.So what operations does the barrel shifter support?LOGICAL SHIFTS LEFT (LSL) – LOGICAL SHIFTS RIGHT (LSR) – ROTATE RIGHT (RR) - Rotate Right Extended (RRX)
- Arithmetic Operations* Operations are:• ADD operand1 + operand2• ADC operand1 + operand2 + carry• SUB operand1 - operand2• SBC operand1 - operand2 + carry -1 • RSB operand2 - operand1• RSC operand2 - operand1 + carry - 1* Syntax:• <Operation>{<cond>}{S} Rd, Rn, Operand2* Examples• ADD r0, r1, r2• SUBGT r3, r3, #1• RSBLES r4, r5, #5Comparisons* The only effect of the comparisons is to• UPDATE THE CONDITION FLAGS. Thus no need to set S bit.* Operations are:• CMP operand1 - operand2, but result not written• CMN operand1 + operand2, but result not written• TST operand1 AND operand2, but result not written• TEQ operand1 EOR operand2, but result not written* Syntax:• <Operation>{<cond>} Rn, Operand2* Examples:• CMP r0, r1• TSTEQ r2, #5Logical Operations* Operations are:• AND operand1 AND operand2• EOR operand1 EOR operand2• ORR operand1 OR operand2• BIC operand1 AND NOT operand2 [ie bit clear]* Syntax:• <Operation>{<cond>}{S} Rd, Rn, Operand2* Examples:• AND r0, r1, r2• BICEQ r2, r3, #7• EORS r1,r3,r0Data Movement* Operations are:• MOV operand2• MVN NOT operand2Note that these make no use of operand1.* Syntax:• <Operation>{<cond>}{S} Rd, Operand2* Examples:• MOV r0, r1• MOVS r2, #10• MVNEQ r1,#0
- Variable cycle execution for certain instructions—Not every ARM instruction executesin a single cycle. For example, load-store-multiple instructions vary in the numberof execution cycles depending upon the number of registers being transferred. Thetransfer can occur on sequentialmemory addresses, which increases performance sincesequential memory accesses are often faster than random accesses. Code density is alsoimproved since multiple register transfers are common operations at the start and endof functions.
- Arithmetic Operations* Operations are:• ADD operand1 + operand2• ADC operand1 + operand2 + carry• SUB operand1 - operand2• SBC operand1 - operand2 + carry -1 • RSB operand2 - operand1• RSC operand2 - operand1 + carry - 1* Syntax:• <Operation>{<cond>}{S} Rd, Rn, Operand2* Examples• ADD r0, r1, r2• SUBGT r3, r3, #1• RSBLES r4, r5, #5Comparisons* The only effect of the comparisons is to• UPDATE THE CONDITION FLAGS. Thus no need to set S bit.* Operations are:• CMP operand1 - operand2, but result not written• CMN operand1 + operand2, but result not written• TST operand1 AND operand2, but result not written• TEQ operand1 EOR operand2, but result not written* Syntax:• <Operation>{<cond>} Rn, Operand2* Examples:• CMP r0, r1• TSTEQ r2, #5Logical Operations* Operations are:• AND operand1 AND operand2• EOR operand1 EOR operand2• ORR operand1 OR operand2• BIC operand1 AND NOT operand2 [ie bit clear]* Syntax:• <Operation>{<cond>}{S} Rd, Rn, Operand2* Examples:• AND r0, r1, r2• BICEQ r2, r3, #7• EORS r1,r3,r0Data Movement* Operations are:• MOV operand2• MVN NOT operand2Note that these make no use of operand1.* Syntax:• <Operation>{<cond>}{S} Rd, Operand2* Examples:• MOV r0, r1• MOVS r2, #10• MVNEQ r1,#0
- The Barrel ShifterA barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle* The ARM doesn’t have actual shift instructions.* Instead it has a barrel shifter which provides a mechanism to carry out shifts as part of other instructions.So what operations does the barrel shifter support?LOGICAL SHIFTS LEFT (LSL) – LOGICAL SHIFTS RIGHT (LSR) – ROTATE RIGHT (RR) - Rotate Right Extended (RRX)
- ARM = RISC, load-store architectures, maksudnyaprosesorhanyaberinteraksidengan memory sebatas load,dan store, tidak support memory untukoperasipemrosesan data memory, harusmemindahkannilai data ke register sebelumdigunakanLoad data values dari memory ke register, data diproses di register menggunakansejumlahinstruksi data processing (nggakdiperlambat memory access), store hasildari register ke memorySingle register data transfer (LDR/STR), block data transfer (LDM/STM), Single Data Swap (SWP)Throughput : jumlah proses yang dapatterjadidalamsatu periodARM = RISC, load-store architectures, maksudnyaprosesorhanyaberinteraksidengan memory sebatas load,dan store, tidak support memory untukoperasipemrosesan data memory, harusmemindahkannilai data ke register sebelumdigunakanLoad data values dari memory ke register, data diproses di register menggunakansejumlahinstruksi data processing (nggakdiperlambat memory access), store hasildari register ke memorySingle register data transfer (LDR/STR), block data transfer (LDM/STM), Single Data Swap (SWP)Throughput : jumlah proses yang dapatterjadidalamsatu period
- Instruksiiniyaitu load/store satu word atau byte dari/kememoridari/ke registerInstruksi : LDR / STR / LDRB / STRB<LDR|STR>{cond}{B}{T} Rd,<Address>Base register berfungsiuntukmenyimpanlokasimemori yang akandiaksesSelagiakseslokasi yang aktual, instruksidapatmengakses offset lokasidari pointerOffset : bisa unsigned 12bit immediate value atau registerPrefix ‘+’ : add. ‘-’ : substractPre-indexed addressing dan post-indexed addressing
- STR r0, [r1, #12]
- Instruksiiniyaitu load/store banyak register dari/kememoridalamsatuwaktu. Dengan kata lain membolehkanantara 1 hingga 16 registers untukditransfer.Instruksi : LDM / STM <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}Register yang ditransferdapatberupa subset dari current bank of registers atau user mode bank of registersMode direct copy dan stack
- Stack Modes Full DescendingFull AscendingEmpty DescendingEmpty AscendingStack adalah areamemori yang berkembangketika data barudipushke top-nya, danmenyusutketikadipopBatas stack ditentukanoleh base pointer dan stack pointerNilai stack pointer dapatberupa last occupied address atau next occupied address
- Menggunakan r12, r13 + r14 sebagai pointer meninggalkan r0-r11 untukpenggunaandalam block copyAkan membutuhkanpenyimpanan r0-r12 + r14 kedalamtumpukan (sehinggadapatmerestorenilaiasliketika copy berakhir). Menyimpan r13 pada word yang diketahuidalam memory jugadapatmenyebabkanhaltersebut (restore).Menggunakaninkremensetelah addressing4 bytes per register (12 registers) => 48 bytes per iteration LDM - 14 cycles STM - 13 cycles CMP - 1 cycle BNE - 3 cycles Total = 31 cycles to move 48 bytes