Parth Pandya
2 SlideShares 3 Seguidores
Personal Information
Organização/Local de trabalho
Hyderabad Area, India India
Cargo
Verification Engineer at Xilinx
Setor
Electronics / Computer Hardware
Sobre
Functional Verification Engineer with experience in development of verification environment, testcases for module and system level verification. Experience in understanding and debugging verilog behavioral design.
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uvm bit bash register model
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UVM Ral model usage

Parth Pandya • Há 9 anos
Personal Information
Organização/Local de trabalho
Hyderabad Area, India India
Cargo
Verification Engineer at Xilinx
Setor
Electronics / Computer Hardware
Sobre
Functional Verification Engineer with experience in development of verification environment, testcases for module and system level verification. Experience in understanding and debugging verilog behavioral design.
Marcadores
uvm bit bash register model
Ver mais