This presentation provides the Hardware Architecture details to understand the Embedded Linux Fundamentals. This also briefs about various hardware & respective interface details of MarsBoard.
9. eMMC Flash
• Flash Memory & MMC Controller into a single
Chip
• Used as embedded non-volatile memory
• Permanent attached to board
• Does not support SPI protocol
• All mobile phone & tablets uses this as
internal memory as well as for images.
11. General Purpose I/O
• Generic Pin on an IC / Board
• Configured as Input or Output
• Can be enabled / disabled
• Logic Level
– High
– Low
• Input values are readable
• Output values are writable / readable
• Input configured pins also can be used as Interrupt
• No predefined purpose
12. Serial Peripheral Interface
• Synchronous Serial Communication Interface
• Used for Short distance. Basically with in the
board
• Full duplex mode with master slave architecture
• Also called as four-wire bus
• Pins
– MISO : Master Input Slave Output
– MOSI : Master Output Slave Input
– SCK : Serial Clock
– SS : Slave Select
14. Inter Integrated Circuit Inteface
• Multi master, multi slave serial interface bus
• Uses only two bi-directional open drain lines
– SDA : Serial Data Line
– SCL : Serial Clock Line
• Since lines are open drain, these pins needs to
be pulled high.
– Normally pull up resistor will be 4.7 K / 10K
20. HDMI
• High Definition Multi Media Interface
• Transfers uncompressed Video, Audio and
Data using a Single Cable
• High bandwidth Data Content Protection
• HDMI System has one to one connectivity with
– HDMI Source which is the transmitter
– HDMI Sinks which is the receiver
• Data Display Channel
– Configuration & Data Exchange in HDMI
22. Parallel RGB LCD Interface
• Parallel Video Interface
• Supports upto 24 Bit Data
• Supports BT.656 Data format ( 8 Bit )
• Supports BT.1120 Data format ( 16 Bit )
• Supports HDTV standards SMPTE274
• Supports HDTV Standards SMPTE296
• RGB Color Depth fully configurable upto 8 Bit /
color value
24. LVDS Display Bridge
• Linear Voltage Differential Signaling
• Used to connect with Display with LVDS receiver
• Featured with Synchronization & Control
• Data arrangement will be based on external
Display
• LVDS Display Port
– 1 Clock Channel
– 4 Data Channel
• Each pair contains LVDS Special differential pads
26. RGMII
• Reduced Giga bit Media Independent Interface
• Used to interface between Ethernet MAC & PHY
• Half the number of data pins used in GMII
• Data clocking will be done at both rising and
falling edges of the clock
• Carrier Sense / Collision Detection
• Management Interface
– Management Interface Clock ( MDC )
– Management Interface I/O ( MDIO )
30. USB OTG
• USB On – The – GO
• Allows devices to switch back & forth between
USB Host & Device
• Will acts as Host when device connected
• Will acts as USB Device when it is connected
with Host
32. Secure JTAG
• Provides debug & test control with maximum
security
• Joint Test Access Group
• IEEE Standard 1149.1 v2001 ( JTAG )
• Debug related control & status
• Putting the selected cores into reset / monitor
• JTAG Boundary Scan
– Provides access to all logic signals of complex IC
– Provides access to device pins