This document discusses different levels of abstraction in Verilog HDL modeling including switch level, gate level, register transfer level (RTL), and behavioral level. It describes modeling techniques like switch-level modeling, gate-level modeling, dataflow modeling, and behavioral modeling. The document also covers key concepts in Verilog like modules, module components, module ports, port assignments, hierarchical design, and module instances. Modules are the basic building blocks in Verilog and allow designers to mix abstraction levels and hierarchically interconnect components.

1. 1
Verilog HDLVerilog HDL
ASIC DESIGN USING
FPGA
BEIT VII
KICSIT
Sep 4 2012 Lecture 5

2. 2
Abstraction Levels
Sep 4 2012
• There are four levels of abstraction
• Switch level
• Gate level
• RTL (Dataflow) level
• Behavioral or algorithmic level
Lecture 5

3. 3
Modeling Techniques
Sep 4 2012
• Switch-Level Modeling
The lowest level of abstraction is the switch
or transistor Level Modeling. (It is rarely
used)
• Gate Level Modeling
It is feasible for small circuits.
Lecture 5

4. 4
Modeling Techniques
Sep 4 2012
• Dataflow Modeling
The level of abstraction higher than the gate
level.
• Behavioral Modeling
In more complex digital designs, priority is
given to the performance and behavior of the
algorithm.
Lecture 5

5. 5
Modeling Techniques
Sep 4 2012
• Verilog allows the designer to mix and match
all four levels of abstractions in a design.
• In the digital design community, the term
register transfer level (RTL) is frequently used
for a Verilog description that uses a
combination of behavioral and dataflow
constructs and is acceptable to logic synthesis
tools.
Lecture 5

6. 6
Modeling Techniques
Sep 4 2012
• Normally, the higher the level of abstraction,
the more flexible and technology-independent
the design.
• As one goes lower toward switch-level design,
the design becomes technology-dependent and
inflexible.
• A small modification can cause a significant
number of changes in the design in Low level
abstration.
Lecture 5

7. 7
Module
Sep 4 2012
• The Module Concept
• The module is the basic building block in
Verilog
• Modules are:
• Declared
• Instantiated
• Modules declarations cannot be nested
Lecture 5

8. 8
Module
Sep 4 2012
• Modules can be interconnected to describe the
structure of your digital system
• Modules start with keyword module and end
with keyword endmodule
• Modules have ports for interconnection with
other modules
Lecture 5

9. 9
Module
Sep 4 2012
•Everything you write in Verilog must be inside
a module exception: compiler directives
Lecture 5

10. 10
Module
Sep 4 2012 Lecture 5

11. 11
Components of a Verilog Module
Sep 4 2012 Lecture 5

12. 12
Components of a Verilog Module
Sep 4 2012 Lecture 5

13. 13
Components of a Verilog Module
Sep 4 2012 Lecture 5
• Stimulus and Design blocks can also be instantiated in a
Dummy Top level module

14. 14
Module Ports
Sep 4 2012
• Similar to pins on a chip
• Provide a way to communicate with outside
world.
• Ports can be input, output or inout
Lecture 5

15. 15
Port Assignments
Sep 4 2012 Lecture 5

16. 16
Hierarchical Design
Sep 4 2012 Lecture 5

17. 17
Module Instances
Sep 4 2012
• Verilog design models consist of a hierarchy
of module instances.
• Like in C++ : modules are classes and
instances are objects.
• The process of creating objects from a module
template is called instantiation.
Lecture 5

18. 18
Module Instances
Sep 4 2012
• As an example a top-level block
ripple_crry_counter creates four instances from
the T-flipflop (T_FF) template.
• Each T_FF instantiates a D_FF and an inverter
gate.
• Each instance must be given a unique name.
Lecture 5

19. 19
Module Instances
Sep 4 2012 Lecture 5