Abstract: Supercomputers have become extremely advanced in computation power. However, the more hardware they are composed of, the higher the failure rate they have, and the more important is to have an ecient fault tolerance solution. The use of FPGAs in computational workloads is becoming increasingly popular due to the exibility of these devices in comparison to ASICs, and their low power consumption compared to GPUs. While they are more complex to develop in than CPUs and GPUs, tools like Vivado HLS (High Level Synthesis) and OmpSs have made the process much easier. Because of that, it is important to know how these devices fair when used along with fault tolerance systems. The main objective of this work is to analyze the performance of the Fault Tolerance Interface (FTI), an ecient multi-level checkpointing library, using a set of applications in a CPU-FPGA heterogeneous environment. With this, we will be able to understand what kind of overheads we can expect from using this library with similarly structured computational workloads. As a side objective, we plan to showcase a proof of concept for checkpointing data inside the FPGA task itself. This can prove useful for workloads in which most data is ooaded to the FPGA memory at once and do not constantly move all the data between the accelerator and the CPU. Poster presented by Marc Perelló Bacardit at the LEGaTO Final Event: 'Low-Energy Heterogeneous Computing Workshop'

1. The LEGaTO project has received funding from the European Union’s Horizon 2020 research
and innovation programme under the grant agreement No 780681. www.legato-project.eu
FPGA Checkpointing using a
Fault Tolerance Interface
Marc Perelló Bacardit