High speed and low power adder circuits are highly demanded in Embedded and VLSI design.
In this paper, a new approach for high speed and low power adder design, with less number of gate counts,
optimization of Area, Power and Delay is proposed, The proposed work presents the design, simulation and
implementation of various 8-bit adders on Cadence Design Suite 6.1.5 with Virtuoso, Assura and ADE toolset,
the designs are implemented in GPDK 45 nm technology with unvaried Width and Length of PMOS and NMOS
device, In this paper the Design and Modelling of Ripple Carry Adder, Carry Skip Adder, Carry Lookahead
Adder and Kogge Stone Adder is done using different design styles like CMOS, GDI and GDI-PTL logic is
applied and comparative analysis ismade. From the simulation results it is clear that Parallel Prefix Adder (KSA)
provide a better result compared to other adder design, the proposed KSA adder is modelled and designed using
the combination of CMOS-GDI logic to give better performance.