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Two voltage (channel 1 and 2) and two current (channel 1 and 2) sensors indicate measured
voltage with 16-bit binary values on their output lines, S15 to S0 .
1. Instantaneous power is a product of voltage and current. Write the behavioral VHDL code to
analyze the power in each channel (1 and 2) and display in 4-bit binary values issuing a 1-bit
address P .
Solution
entity power is
begin
port(V1,V2,I1,I2:in std_logic_vector(15 downto 0); P1,P2: out std_logic_vector(3 downto 0));
end entity;
architecture arc_power of power is
signal P1_temp,P2_temp: std_logic_vector(15 downto 0);
signal pt1,pt2,pt3,pt4,p1,p2,p3,p4: bit;
begin
P1_temp<=V1 and I1;
P2_temp<=V2 and I2;
pt1<=P1_temp[3] or P1_temp[2] or P1_temp[1] or P1_temp[0];
pt2<=P1_temp[7] or P1_temp[6] or P1_temp[5] or P1_temp[4];
pt3<=P1_temp[11] or P1_temp[10] or P1_temp[9] or P1_temp[8];
pt4<=P1_temp[15] or P1_temp[14] or P1_temp[13] or P1_temp[12];
P1<=pt4&pt3&pt2&pt1;
p1<=P2_temp[3] or P2_temp[2] or P2_temp[1] or P2_temp[0];
p2<=P2_temp[7] or P2_temp[6] or P2_temp[5] or P2_temp[4];
p3<=P2_temp[11] or P2_temp[10] or P2_temp[9] or P2_temp[8];
p4<=P2_temp[15] or P2_temp[14] or P2_temp[13] or P2_temp[12];
P2<=p4&p3&p2&p1;
end architecture;

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Two voltage (channel 1 and 2) and two current (channel 1 and 2) sensor.docx

  • 1. Two voltage (channel 1 and 2) and two current (channel 1 and 2) sensors indicate measured voltage with 16-bit binary values on their output lines, S15 to S0 . 1. Instantaneous power is a product of voltage and current. Write the behavioral VHDL code to analyze the power in each channel (1 and 2) and display in 4-bit binary values issuing a 1-bit address P . Solution entity power is begin port(V1,V2,I1,I2:in std_logic_vector(15 downto 0); P1,P2: out std_logic_vector(3 downto 0)); end entity; architecture arc_power of power is signal P1_temp,P2_temp: std_logic_vector(15 downto 0); signal pt1,pt2,pt3,pt4,p1,p2,p3,p4: bit; begin P1_temp<=V1 and I1; P2_temp<=V2 and I2; pt1<=P1_temp[3] or P1_temp[2] or P1_temp[1] or P1_temp[0]; pt2<=P1_temp[7] or P1_temp[6] or P1_temp[5] or P1_temp[4]; pt3<=P1_temp[11] or P1_temp[10] or P1_temp[9] or P1_temp[8]; pt4<=P1_temp[15] or P1_temp[14] or P1_temp[13] or P1_temp[12];
  • 2. P1<=pt4&pt3&pt2&pt1; p1<=P2_temp[3] or P2_temp[2] or P2_temp[1] or P2_temp[0]; p2<=P2_temp[7] or P2_temp[6] or P2_temp[5] or P2_temp[4]; p3<=P2_temp[11] or P2_temp[10] or P2_temp[9] or P2_temp[8]; p4<=P2_temp[15] or P2_temp[14] or P2_temp[13] or P2_temp[12]; P2<=p4&p3&p2&p1; end architecture;