This chapter discusses static CMOS circuits. It covers the goals of optimizing gate metrics like area, speed, energy and robustness. It discusses static CMOS logic families and high-performance circuit design techniques. Static CMOS circuits keep each gate output connected to either VDD or VSS at all times, unlike dynamic circuits which rely on temporary signal storage. The chapter explains how to construct static CMOS gates using pull-up and pull-down networks and discusses transistor sizing to optimize performance.

1. Chapter 6
Static CMOS Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August , 2004; Revised - June 28, 2005

2. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 2
Goals of This Chapter
 In-depth discussion of CMOS logic families
 Static and Dynamic
 Pass-Transistor
 Nonratioed and Ratioed Logic
 Optimizing gate metrics
 Area, Speed, Energy or Robustness
 High Performance circuit-design techniques

3. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 3
Combinational Sequential
Output = f(In)
Combinational
Logic
Circuit
Out
In
Combinational
Logic
Circuit
Out
In
State
Output = f(In, Previous In)
Combinational vs. Sequential Logic

4. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 4
Static CMOS Circuits
 At every point in time (except during the switching
transients) each gate output is connected to either
VDD or VSS via a low-resistance path.
 The outputs of the gates assume at all times the
value of the Boolean function, implemented by the
circuit (ignoring, once again, the transient effects
during switching periods)
 This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes

5. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 5
PUN and PDN are dual logic networks
F(In1,In2,…InN)
VDD
In1
PUN
PDN
In2
InN
In1
In2
InN
Static Complementary CMOS
PMOS transistors only
NMOS transistors only
Pull-Up Network: make a connection
from VDD to F when F(In1,In2,…InN) = 1
Pull-Down Network: make a connection
from F to GND when F(In1,In2,…InN) = 0

6. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 6
Threshold Drops
PDN
PUN
CL
VDD 
VDD
0 
CL
VDD
VDD
VDD 
CL
0 
VDD
CL
S
D
S
D S
D
VGS
S
D
VGS
VDD VDD - VTn
0 |VTp|

7. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 7
A
B
A B
Construction of PDN
 Transistors can be thought as a switch controlled by its
gate signal
 NMOS switch closes when switch control input is high
NMOS Transistors pass a “strong” 0 but a “weak” 1
A • B
Series = NAND
A + B
Parallel = NOR

8. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 8
Construction of PUN
 PMOS switch closes when switch control input is low.
PMOS Transistors pass a “strong” 0 but a “weak” 1
A
B
A B
Series = NOR
A • B = A + B
Parallel = NAND
A + B = A • B

9. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 9
Duality of PUN and PDN
 PUN and PDN are dual networks
 De Morgan’s theorems
 A parallel connection of transistors in the PUN
corresponds to a series connection of the PDN
 Complementary gate is naturally inverting
(NAND, NOR, AOI, OAI)
 Number of transistors for an N-input logic gate is 2N
A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]
A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]

10. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 10
A • B
A
B
A B
A B F
0 0 1
0 1 1
1 0 1
1 1 0
Example: CMOS NAND gate
VDD
A
B
F
PDN: G = A · B
PUN: F = A + B
Conduction to GND
Conduction to VDD
G(In1, In2, …, InN) = F(In1, In2, …, InN)

11. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 11
Example: CMOS NOR gate
A + B
A
B
A B
VDD A B F
0 0 1
0 1 0
1 0 0
1 1 0
A
B
F

12. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 12
D
A
B C
D
A
B
C
OUT = D + A • (B + C)
Complex CMOS Gate
Derive PUN hierarchically
by identifying sub-nets

13. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 13
Cell Design: An Introduction
 Standard Cells
 A general purpose logic
 Synthesizable
 Same height but varying width
 Datapath Cells
 For regular, structured designs (arithmetic)
 Including some wiring in the cell
 Fixed height and width

14. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 14
Example of A Standard Cell
Cell boundary
N Well
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch = repetitive distance
between objects
2
Rails ~10
In
Out
VDD
GND
Cell height is “12 pitch”
Minimum-Size
Inverter

15. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 15
signals
Routing channel
VDD
GND
Standard Cell Layout Methodology – 1980s
Routing channel
What logic function is this?

16. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 16
M2
No Routing
channels
VDD
GND
M3
VDD
GND
Mirrored Cell
Mirrored Cell
Standard Cell Layout Methodology – 1990s

17. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 17
Contains no dimensions
Represents relative positions of transistors
Inverter
In
Out
VDD
GND
NAND2
A
Out
VDD
GND
B
Stick Diagrams

18. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 18
OAI21 Logic Graph
C
A B
B
A
C
i
j
j
VDD
X
X
i
GND
A
B
C
PUN
PDN
A
B
C
X = C • (A + B)
Node of the
circuit
Transition
Control

19. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 19
Two Stick Diagrams of C • (A + B)
A B C
X
VDD
GND
X
C
A B
VDD
GND
Crossover can be eliminated by re-ordering inputs

20. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 20
j
VDD
X
X
i
GND
A
B
C
A B C
 For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
Consistent Euler Path
 An uninterrupted diffusion strip is possible only if there
exists an Euler path in the logic graph
Euler path: a path through all
nodes in the graph such that
each edge is visited once and
only once.

21. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 21
A
B
C
D
C
A B
B
A
D
C
D
X = (A+B)•(C+D)
VDD
X
X
GND
A
B
C
PUN
PDN
D
OAI22 Logic Graph

22. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 22
B
A D
VDD
GND
C
X
 Some functions have no consistent Euler path like
x = !(a + bc + de) (but x = !(bc + a + de) does!)
OAI22 Layout

23. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 23
A
B
A  B
XNOR XOR
A
B
A  B A  B
A
B
A
B
A  B
 How many transistor in each?
 Can you create the stick diagrams for the lower left circuit?
XNOR/XOR Implementation

24. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 24
VGS2 = VA –VDS1
VGS1 = VB
M1
M2
M3 M4
A
B
F= A • B
A B
Cint
D
D
S
S
0.5/0.25 NMOS
0.75 /0.25 PMOS
weaker
PUN
VTC Characteristics are dependent upon the data input patterns
applied to the gate (so the noise margins are also data dependent!)
VTC is Data-Dependent

25. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 25
Observation I
 The difference between the blue and the orange
lines results from the state of internal node int
between the two NMOS Devices.
 The threshold voltage of M2 is higher than M1
due to the body effect (),
 VSB of M2 is not zero (when VB = 0) due to the
presence of Cint
VTn1 = VTn0 and VTn2 = VTn0 + ((|2F| + Vint) - |2F|)

26. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 26
Review: CMOS Inverter - Dynamic
tpHL = f(Rn, CL)
tpHL = 0.69 Reqn CL
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.52 CL / (W/Ln k’n VDSATn )
VDD
Rn
Vout
Vin = V DD
CL
propagation delay is determined by the time to
charge and discharge the load capacitor CL

27. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 27
Review: Designing for Performance
 Reduce CL
 Increase W/L ratio of the transistor
 the most powerful and effective performance optimization tool
 watch out for self-loading!
 Increase VDD
 only minimal improvement in performance at the cost of
increased energy dissipation
 Slope engineering - keeping signal rise and fall times
smaller than or equal to the gate propagation delays and
of approximately equal values
 good for performance and power consumption

28. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 28
A
Req
A
CL
A
Rn
A
Rp
B
Rp
B
Rn Cint
NAND
Rp
A
A
Rn CL
INVERTER
Rp
Rp
Rn Rn CL
Cint
B
A
A B
NOR
Switch Delay Model

29. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 29
Input Pattern Effects on Delay
 Delay is dependent on the pattern of inputs
 Low to high transition
 both inputs go low
 delay is 0.69 Rp/2 CL since two p-resistors are
on in parallel
 one input goes low
 delay is 0.69 Rp CL
 High to low transition
 both inputs go high
 delay is 0.69 2Rn CL
 Adding transistors in series (without sizing)
slows down the circuit
CL
A
Rn
A
Rp
B
Rp
B
Rn Cint
NAND

30. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 30
Delay Dependence on Input Patterns
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
Voltage
[V]
Input Data
Pattern
Delay
(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5m/0.25 m, PMOS = 0.75m/0.25 m, CL = 100 fF

31. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 31
Transistor Sizing Basic
 Inverter as a reference circuit
Device Transconductance
(See Supplement 1)
kn = kn’(W/L)n = (µnox/tox)((W/L)n
kp = kp’(W/L)p = (µpox/tox)((W/L)p
For rise time equal to fall time,
kp = kn (Rp = Rn)
Out
In
VDD
(W/L)p
(W/L)n
CL
Because µp ~ µn /2
(W/L)p = 2 (W/L)n
The size of PMOS must be twice as large as that of NMOS
2
1

32. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 32
Transistor Sizing: NAND and NOR
2
2
2 2
1
1
4
4
CL
A
Rn
A
Rp
B
Rp
B
Rn Cint
NAND
Rp
Rp
Rn Rn CL
Cint
B
A
A B
NOR
Symmetric Response RPUN = RPDN
Rp  1/(W/L)p
Rn  1/(W/L)n
RPDN = Rn + Rn
RPUN = Rp + Rp

33. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 33
Note on Transistor Sizing
 By assuming RPUN = RPDN, we ignores the extra
diffusion capacitance introduced by widening
the transistors.
 In DSM, even larger increases in the width are
needed due to velocity saturation.
 For 2-input NANDs, the NMOS transistors should
be made 2.5 times as wide.
 NAND implementation is clearly preferred
over a NOR implementation, since a PMOS
stack series is slower than an NMOS stack due
to lower carrier mobility

34. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 34
1
2
2 2
4
4
8
8
Transistor Sizing: Complex CMOS Gate
D
A
B C
D
A
B
C
6
6
12
12
 Red sizing assuming RPUN = RPDN
 Follow short path first; note PMOS
for C and B,4 rather than 3 (average
in pull-up chain of three =
(4+4+2)/3)
 Also note structure of pull-up and
pull-down to minimize diffusion
cap. at output (e.g., single PMOS
drain connected to output)
 Green for symmetric response and
for performance (where Rp = 3Rn)
 Sizing rules of thumb: PMOS = 3
* NMOS

35. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 35
Fan-In Considerations
D
C
B
A
D
C
B
A CL
C3
C2
C1
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of
fan-in – quadratically in the worst case.

36. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 36
Notes on Fan-In Considerations
 While output capacitance makes full swing transition from
VDD to 0, internal nodes only swing from VDD-VTn to GND
 C1, C2, and C3, each includes junction capacitance as well
as the gate-to-source and gate-to-drain capacitances
(turned into capacitances to ground using the Miller effect)
 For W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, values are on
the order of 0.85 fF
 CL = 3.47 fF with NO output load (all of diffusion
capacitance = intrinsic capacitance of the gate itself).
 tpHL = 85 ps (simulated as 86 ps).
 The simulated worst case low-to-high delay was 106 ps.

37. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 37
tp as a Function of Fan-In
Gates with a fan-in greater than 4 should be avoided.
quadratic
linear
tpLH
t
p
(psec)
fan-in
tpHL tp

38. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 38
tp as a Function of Fan-Out
All gates have the same drive current.
tpNOR2
t
p
(psec)
eff. fan-out
tpNAND2
tpINV
Slope is a function of “driving strength”

39. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 39
tp as a Function of Fan-In and Fan-Out
 Fan-in: quadratic due to increasing resistance
and capacitance
 Fan-out: each additional fan-out gate adds two
gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
Parallel Chain Serial Chain

40. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 40
Distributed RC line
M1 > M2 > M3 > … > MN
(the FET closest to the output
should be the smallest)
Can reduce delay by more
than 20%; decreasing gains
as technology shrinks
Fast Complex Gates: Design Technique 1
 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
InN CL
C3
C2
C1
In1
In2
In3
M1
M2
M3
MN

41. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 41
Notes on Design Technique 1
 With transistor sizing, if the load capacitance is dominated
by the intrinsic capacitance of the gate, widening the device
only creates a “self loading” effect and the propagation
delay is unaffected (and may even become worse).
 For progressive sizing, M1 have to carry the discharge
current from M2 (C1), M3 (C2), … MN and CL so make it
the largest.
 MN only has to discharge the current from MN (CL)(no internal
capacitances).
 While progressive sizing is easy in a schematic, in a real
layout it may not pay off due to design-rule considerations
that force the designer to push the transistors apart
 increasing internal capacitance.

42. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 42
charged
charged
delay determined by time
to discharge CL, C1 and C2
delay determined by time
to discharge CL
discharged
discharged
Fast Complex Gates: Design Technique 2
 Input re-ordering
 when not all inputs arrive at the same time
CL
C2
C1
In3
In2
In1
M1
M2
M3
critical path
1
1
01 charged
CL
C2
C1
In1
In2
In3
M1
M2
M3
critical path
1
01
charged
1
Place latest arriving signal (critical path)
closest to the output can result in a speed up.

43. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 43
Example: Sizing and Ordering Effects
D
C
B
A
D
C
B
A CL = 100 fF
C3
C2
C1
3 3 3 3
4
4
4
4
4
5
6
7
Progressive sizing in pull-down
chain gives up to a 23%
improvement.
Input ordering saves 5%
critical path A – 23%
critical path D – 17%

44. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 44
F = ABCDEFGH
Fast Complex Gates: Design Technique 3
 Alternative logic structures
 Reduced fan-in results in deeper logic depth
Reduction in fan-in offsets, by far, the
extra delay incurred by the NOR gate.

45. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 45
Notes on Design Technique 3
 Reducing fan-in increases logic depth of the
circuit
 More stages but each stage has smaller delay
 Only simulation will tell which of the two
alternative configurations is faster and has lower
power dissipation.

46. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 46
CL
CL
Fast Complex Gates: Design Technique 4
 Isolating fan-in from fan-out using buffer
insertion
 Optimizing the propagation delay of a gate in isolation
is misguided.
Reduce CL on large fan-in gates, especially for large CL,
and size the inverters progressively to handle the CL
more effectively

47. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 47
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
Fast Complex Gates: Design Technique 5
 Reducing the voltage swing
 linear reduction in delay
 also reduces power consumption
 But the following gate is much slower!
 Or requires the use of “sense amplifiers” on the
receiving end to restore the signal level (memory
design)

48. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 48
Sizing Logic Paths for Speed
 Frequently, input capacitance of a logic path is
constrained
 Logic also has to drive some capacitance
 Example: ALU load in an Intel’s microprocessor is
0.5pF
 How do we size the ALU data path to achieve
maximum speed?
 We have already solved this for the inverter chain
– can we generalize it for any type of logic?

49. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 49
Inverter Chain: Recap
CL
In Out
1 2 N
1 f f N-1
For given N: Ci+1/Ci = Ci/Ci-1 = f = (CL/Cin)
N
 For optimum performance, we try to keep f ~ 4,
which give us the number of stages, N.
 Can the same approach (logical effort) be used
for any combinational circuit?

50. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 50
Delay of a Complex Logic Gate
 For a complex gate, we expand the inverter chain equation
 tp0 is the intrinsic delay of an inverter
 f is the effective fan-out (Cext/Cg) - also called the
electrical effort
 p is the ratio of the intrinsic (unloaded) delay of the
complex gate and a simple inverter (a function of the
gate topology and layout style)
 g is the logical effort

51. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 51
Notes on Delay of a Logic Gate
Gate delay: D = h + p
Effort delay Intrinsic delay
Effort delay: h = g f
Logical
Effort
Electrical
Effort
(effective fan-out)
 Logical effort first defined by Sutherland and
Sproull in 1999.
 In a simpler format,
= Cout/Cin

52. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 52
Intrinsic Delay Term, p
 The more involved the structure of the complex
gate, the higher the intrinsic delay compared to
an inverter
Ignoring second order effects such as internal node capacitances
Gate Type p
Inverter 1
n-input NAND n
n-input NOR n
n-way mux 2n
XOR, XNOR n 2n-1

53. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 53
Logical Effort Term, g
 Logical effort of a gate, g, presents the ratio of its input
capacitance to the inverter capacitance when sized to
deliver the same current
 g represents the fact that, for a given load, complex gates have
to work harder than an inverter to produce a similar (speed)
response
Gate Type
g (for 1 to 4 input gates)
1 2 3 4
Inverter 1
NAND 4/3 5/3 (n+2)/3
NOR 5/3 7/3 (2n+1)/3
Mux 2 2 2
XOR 4 12

54. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 54
Notes on Logical Effort
 Inverter has the smallest logical effort and intrinsic delay
of all static CMOS gates
 Logical effort of a gate tells how much worse it is at
producing an output current than an inverter (how much
more input capacitance a gate presents to deliver same
output current)
 Logical effort is a function of topology, independent of
sizing
 Logical effort increases with the gate complexity
 Electrical effort (Effective fanout) is a function of
load/gate size

55. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 55
A + B
A
B
A B
A
A
A
2
1
Cunit = 3
2 2
2
2
Cunit = 4
4
4
1 1
Cunit = 5
Example of Logical Effort
 Assuming a PMOS/NMOS ratio of 2, the input
capacitance of a minimum-sized inverter is three times
the gate capacitance of a minimum-sized NMOS (Cunit)
A • B
A
B
A B

56. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 56
Delay as a Function of Fan-Out
 The slope of the line is
the logical effort of the
gate
 The y-axis intercept is
the intrinsic delay
 Can adjust the delay by
adjusting the effective
fan-out (by sizing) or
by choosing a gate with
a different logical effort
normalized
delay
fan-out f
intrinsic delay
effort delay
Gate Effort: h = fg

57. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 57
1
a b c
CL
5
Path Delay: Complex Logic Gate Network
 Total path delay through a combinational logic block
tp =  tp,j = tp0 (pj + (fj gj)/ )
 So, the minimum delay through the path determines that
each stage should bear the same gate effort
f1g1 = f2g2 = . . . = fNgN
 Consider optimizing the delay through the logic network
how do we determine a, b, and c sizes?

58. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 58
Path Delay Equation Derivation
 The path logical effort, G =  gi
 And the path effective fan-out (path electrical effort) is
F = CL/g1
 The branching effort accounts for fan-out to other
gates in the network
b = (Con-path + Coff-path)/Con-path
 The path branching effort is then B =  bi
 The total path effort is then H = GFB
 So, the minimum delay through the path is
N
D = tp0 ( pj + (N H)/ )

59. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 59
Example: Complex Logic Gates
 For gate i in the chain, its size is determined by
 For this network
 F = CL/Cg1 = 5
 G = 1 x 5/3 x 5/3 x 1 = 25/9
 B = 1 (no branching)
 H = GFB = 125/9, so the optimal stage effort is H = 1.93
 Fan-out factors are f1=1.93, f2=1.93 x 3/5 = 1.16, f3 = 1.16, f4 = 1.93
 So the gate sizes are a = f1g1/g2 = 1.16, b = f1f2g1/g3 = 1.34 and
c = f1f2f3g1/g4 = 2.60
4
j=1
i -1
si = (g1 s1)/gi  (fj/bj)
1
a b c
CL
5

60. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 60
Example – 8-input AND

61. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 61
Summary: Method of Logical Effort
 Compute the path effort: F = GBH
 Find the best number of stages N ~ log4F
 Compute the stage effort f = F1/N
 Sketch the path with this number of stages
 Work either from either end, find sizes:
Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

62. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 62
Summary: Key Definitions
Sutherland,
Sproull
Harris

63. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 63
VDD
VSS
PDN
In1
In2
In3
F
RL
Load
Resistive
N transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
Ratioed Logic
 N transistors + Load
 VOH = VDD
 VOL = RPDN / (RPDN + RL)
 Asymmetrical Response
 Static Power
consumption Plow
 tpL = 0.69 RLCL
Goal: To Reduce the number of devices over complementary CMOS

64. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 64
VDD
VSS
In1
In2
In3
F
VDD
VSS
PDN
In1
In2
In3
F
VSS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudo-NMOS
VT < 0
Ratioed Logic: Active Loads
VDD
VSS
In1
In2
In3
F
VDD
VSS
PDN
In1
In2
In3
F
VSS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudo-NMOS
VT < 0

65. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 65
Pseudo NMOS NAND and NOR
D
C
B
A CL
F
NAND
D
C
B
A CL
F
NOR
 Psedo-NMOS is useful when area is
most important
 Reduce transistor counts
 Used occasionally for large fan-in gates

66. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 66
Pseudo-NMOS Inverter Characteristics
 Assumptions:
 NMOS resides in linear mode
 VOL is small relative to the gate drive (VDD-VT))

67. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 67
Pseudo-NMOS Inverter VTC
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
W/Lp = 4
W/Lp
= 2
W/Lp
= 1
W/Lp= 0.25
W/Lp
= 0.5
V
out
(V)
Vin (V)
Size
VOL
(V)
Pstat
(µW)
tpLH
(ps)
4 0.693 564 14
2 0.273 298 56
1 0.133 160 123
0.5 0.064 80 268
0.25 0.031 41 569
NMOS size = 0.5 µm/0.25 µm
Larger pull-up device not only improves performance (delay)
but also increases power dissipation and lowers noise margins
by increasing VOL

68. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 68
 M1 >> M2
 The idea is to reduce
static power consump-
tion by adjusting the
load
 Load M2 when there are
not too many inputs
(A, B, C, or D) active
 Switch to Load M1
when all inputs are
active (thus require high
amount of current to
drive)
Improved Loads: Adaptive Load
A B C D
F
CL
M1
M2 M1 >> M2
Enable
VDD
Adaptive Load
Enable

69. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 69
Improved Loads: DCVSL
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
A
A
B
B
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)

70. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 70
B
A A
B B B
Out
Out
XOR-NXOR gate
DCVSL Example

71. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 71
DCVSL Characteristics
 Dual Rail Logic
 Each input is provided in complementary format and each gate
produces complementary output
 Increasing complexity
 Rail-to-Rail Swing
 No static power dissipation
 Sizing of the PMOS relative to PDN is critical to
functionality, not just performance
 PDNs must be strong enough to bring outputs below
VDD - |VTp|

72. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 72
DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0
-0.5
0.5
1.5
2.5
Time [ns]
V
olta
g
e
[V]
A B
A B
A,B
A,B
Transient Response of a 2-input AND/NAND gate. How does it look like?
tin->out = 197 ps
tin->out = 321 ps

73. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 73
A B
X Y
X = Y if A and B
X Y
A
B X = Y if A or B
NMOS Transistors in Series/Parallel
 Primary inputs drive both gate and source/drain terminals
 NMOS switch closes when the gate input is high
Remember - NMOS transistors pass a strong 0 but a weak 1

74. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 74
PMOS Transistors in Series/Parallel
 Primary inputs drive both gate and source/drain terminals
 PMOS switch closes when the gate input is low
Remember - PMOS transistors pass a strong 1 but a weak 0
X = Y if A and B = A + B
X = Y if A or B = A  B
A B
X Y
X Y
A
B

75. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 76
A
0
B
B F= AB
0.5/0.25
0.5/0.25
0.5/0.25
1.5/0.25
B = VDD, A = 0VDD
A = VDD, B = 0VDD
A = B = 0VDD
V
out
,
(V)
 Pure PT logic is not regenerative - the signal
gradually degrades after passing through a number
of PTs (can fix with static CMOS inverter insertion)
VTC of PT AND Gate

76. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 77
Complementary PT Logic (CPL)
B
A
A
B PT Network F
F
B
A
A
B
Inverse
PT Network F
F
A
A
B F=A+B
B
B
B
OR/NOR
F=A+B
A
A
B F=A·B
B
B
B
AND/NAND
F=A·B
F=AB
F=AB
A
A
A
A
B
B
XOR/XNOR

77. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 78
CPL Properties
 Differential, so complementary data inputs and outputs are
always available (don’t need extra inverters)
 Static, since the output defining nodes are always tied to
VDD or GND through a low resistance path
 Design is modular; all gates use the same topology, only
the inputs are permuted.
 Simple XOR makes it attractive for structures like adders
 Fast! (assuming number of transistors in series is small)
 Additional routing overhead for complementary signals
 Still have static power dissipation problems

78. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 79
NMOS-Only PT Driving an Inverter
 Threshold voltage drop causes static power consumption
(M2 may be weakly conducting forming a path from
VDD to GND)
 Notice VTn increases of pass transistor due to body effect
(VSB)
Vx does not pull up to VDD, but VDD – VTn
VGS
In = VDD
A = VDD
Vx
M1
M2
B
S
D Out

79. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 80
Voltage Swing of PT Driving an Inverter
 Body effect – large VSB at X - when pulling high (B is tied
to GND and S charged up close to VDD)
 So the voltage drop is even worse
Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
Time (ns)
Voltage
(V)
In
Out
X = 1.8V
In = 0  VDD
VDD
X
Out
0.5/0.25
0.5/0.25
1.5/0.25
D
S
B

80. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 81
Cascaded NMOS-Only PTs
B =
VDD
Out
M
1
y
M2
A = VDD
C =
VDD
x
G
S
G
S
x
M1
B =
VDD
Out
y
M2
C = VDD
A = VDD
= VDD - VTn1
Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1
 Pass transistor gates should never be cascaded as on
the left
 Logic on the right suffers from static power
dissipation and reduced noise margins

81. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 82
M1
M2
A Mn
x
B
Out
Solution 1: Level Restorer
 For correct operation Mr
must be sized correctly
(ratioed)
 Full swing on x (due to
Level Restorer) so no static
power consumption by
inverter
 No static backward current
path through Level Restorer
and PT since Restorer is
only active when A is high
Level
Restorer
Mr
A B X Out Mr
0 0VDD 0 VDD OFF
VDD 0VDD VDD 0 ON

82. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 83
Transient Level Restorer Circuit Response
Voltage
(V)
Time (ps)
W/Lr=1.75/0.25
W/Lr=1.50/0.25
W/Lr=1.25/0.25
W/Lr=1.0/0.25
node x never goes below
VM of inverter so output
never switches
 Restorer has speed and power impacts:
 Increases the capacitance at x, slowing down the gate
 Increases tr (but decreases tf)
W/Ln=0.50/0.25, W/L1=0.50/0.25, W/L2=1.50/0.25

83. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 84
Notes on Level Restorer
 Pull down must be stronger than restorer (pull up)
to switch node X
 If resistance of restorer transistor is too small (too
wide transistor) it is impossible to bring the
voltage at node X below the switching threshold of
the inverter, and the inverter never switches!
 Sizing of Mr is critical for DC functionality, not
just performance!!
 It belongs to Dynamic Logic Family

84. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 85
Solution 2: Multiple VT Transistors
 Technology solution: Use (near) zero VT devices for
the NMOS PTs to eliminate most of the threshold drop
(body effect still in force preventing full swing to VDD)
Out
In2 = 0V
In1 = 2.5V
A = 2.5V
B = 0V
low VT
transistors
sneak
path
on
off but
leaking
Watch out for subthreshold
current flowing through PTs

85. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 86
Solution 3: Transmission Gates (TGs)
 Full swing bidirectional switch controlled by the gate
signal C, A = B if C = 1
A B
C
C
B
C = VDD
C = GND
A = VDD B
C = VDD
C = GND
A = GND
 Most widely used solution
A B
C
C

86. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 87
Resistance of TG
Resistance
(k)
Rp
Rn
Req
Rp
Rn
2.5V
0V
2.5V Vout
W/Ln=0.50/0.25
W/Lp=0.50/0.25
 TG is not an ideal switch - series resistance
 Req is relatively constant ( about 8kohms in this case),
so can assume has a constant resistance
Req = Rp || Rn

87. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 88
S
S
S
In2
In1
F
F = !(In1  S + In2  S)
GND
VDD
In1 In2
S S
S S F
TG Multiplexer

88. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 89
off
off
B
A A  B
Transmission Gate XOR
 F always has a connection to VDD or GND - not dynamic
 No voltage drop
6 Transistors

89. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 90
Transmission Gate XOR
B
A F = A‘
VDD (B)
0 (B’)
 When B = 1, the circuit behaves as if it is an inverter,
hence F(B = 1) = A’
off
off
1

90. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 91
Transmission Gate XOR
 When B = 0, the circuit acts as a transmission gate,
hence F(B = 0) = A (TG ensures no voltage drop)
B
A F = A
when A = 0
weak 0
weak 1
when A = 1
VDD (B’)
0 (B)
on
on
0

91. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 92
Transmission Gate XOR
B
A A‘ B + A B’
 Combine the results using Shannon’s expansion theorem,
F = B·F(B = 1) + B’·F(B = 0) = A’B+AB’ = A  B

92. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 93
TG Full Adder
Sum
Cout
A
B
Cin
• 16 Transistors, no more than 2 PTs in series
• Full swing
• Similar delay for Sum and Carry

93. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 95
Delay of a TG Chain
C C C C
VN
V1 Vi Vi+1
5
0
5
0
5
0
5
0
Vin
 Delay of the RC chain (N TG’s in series) is
tp(Vn) = 0.69 kCReq = 0.69 CReq (N(N+1))/2  0.35 CReqN2
Req Req Req Req
Vin
C C C C
V1 Vi Vi+1
VN

94. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 96
Notes on TG Chain Delay
 Delay grows quadratically in N (in this case in the
number of TGs in series) and increases rapidly with the
number of switches in the chain.
 E.g., for 16 cascaded minimum-sized TG’s, each with an
Req of 8kohms.
 The node capacitance is the sum of the capacitances of two
NMOS and PMOS devices (junctions and drains).
 Capacitance values is approx. 3.6 fF for low to high transitions.
 The delay through the chain is
 tp = 0.69 CReq(N(N+1))/2 = 0.69 x 3.6fF x 8kΩ x (16x17)/2
= 2.7ns

95. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 97
 Delay of buffered chain (M TG’s between buffer)
tp = 0.69 N/M CReq (M(M+1))/2 + (N/M - 1) tpbuf
Mopt = 1.7  (tpbuf/CReq )  3 or 4
TG Delay Optimization
 Can speed it up by inserting buffers every M switches
Vin
VN
M
C
5
0
5
0
5
0
C C
5
0
5
0
5
0
C C
C

96. B.Supmonchai
2102-545 Digital ICs Static CMOS Circuits 98
Notes on Delay Optimization
 Buffered chain is now linear in N
 Quadratic in M but M should be small
 This buffer insertion technique works to speed up the
delay down long wires as well.
 Consider 16TG chain example. Buffers = inverters
(making sure correct polarity is output).
 For 0.5micron/0.25micron NMOSs and PMOSs in the TGs,
 simulated delay with 2TG per buffer is 154 ps,
 for 3TGs is 154ps, and for 4TG is 164ps.
 The insertion of buffering inverters reduces the delay by a
factor of almost 2.