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1. Minimum Parallel Binary Adders with NOR (NAND) Gates
ABSTRACT:
Parallel binary adders of n bits long in single-rail input logic which have a
minimum number of NOR gates are derived in this paper. The minimality of the
number of NOR gates is proved for an arbitrary value of n. Also, it is proved that
the adders must be a cascade of basic modules and that there exist many different
types of basic modules. These adders have fewer gates and shorter net gate delays
(or fewer connections) than the widely used carry-ripple adders which are a
cascade of one-bit full adders. Design procedures of such adders are described,
based on the integer-programming logic design method. There are many solutions
but adders with few connections and those with few net gate delays (all these
adders have the minimum number of gates) are shown as important examples.
Altbough these adders are designed with NOR gates, the results in this paper are
applicable to adders with NAND gates by duality conversion.

2. EXISTING SYSTEM:
A parallel binary adder of n-bits constructed by cascading n stages of one-bit full
adders is called a carry ripple adder. Although carry-ripple adders are usually used
where a high-speed adder is not required or the compactness of a network -is most
important,- the carry-ripple adder is faster than the carry-look-ahead adder [6] in
some electronic implementation (e.g., the carry-ripple adder was preferred for high
speed in Intel's MOS microprocessor 8080 [2] due to greater parasitic capacitance
of the carry-look-ahead adder). Because of the importance of one-bit full adders,
minimum logic networks realizing one-bit full adders have been studied for some
time. Minimum one-bit full adders with NAND (or NOR) gates can be found in
[1], [7], [4]. Also minimum one-bit full adders with NOR, NAND, AND, and OR
gates under various types of restrictions were solved [4] by using the integer
programming logic design method [10], [11], [8]. It should be noted that these
networks have a minimum number of gates only for one-bitfull adders and may not
necessarily be basic units of a parallel binary adder of n-bits with a minimum
number of gates. In the case of a parallel binary adder of n-bits, it should be noted
that carries ci in (1.1) need not be explicitly produced. Majerski and Wiweger [12],
and Quatse and Keir [15] showed one-bit binary adder modules with NOR gates in
each of which the carry is not represented by a single line, but by two or four lines

3. (only in the case of double-rail input logic without proving the minimality of the
number of gates unlike our discussion in this paper, though).
In other words, ci+1 itself is not an output of such a module, but the module
has two outputs (or four outputs), in addition to the output for si, such that the
disjunction of the two expresses the carry signal (and its complement, if four
outputs). For this reason such an adder module will not be called a one-bitfull
adder but a one-bit adder module. It can be shown that a parallel adder consisting
of such adder modules consists of fewer gates and has fewer net gate delays or
fewer connections than the widely used conventional carry-ripple adder.
PROPOSED SYSTEM:
The compactness of networks is becoming more important since the cost of an LSI
chip depends largely on the chip size and also the production yield which is closely
related to the chip size. Furthermore, a more compact network can often increase
the speed because of its lower parasitic capacitance. In actual logic design, the chip
area occupied by a network cannot be known until the actual layout is made. Based
on some computational results, it is concluded in [9] that the minimization of the
number of gates as the primary objective and the number of connections as the
secondary objective usually yields most compact networks even in the case of LSI,

4. at least for functions of a small number of variables. However, since obtaining
minimum networks for
functions which require a large number of gates is computationally infeasible (e.g.,
[4], [9], [1], [7, p. 42]), minimum networks for parallel adders of a large number of
bits have not yet been obtained despite their significance. In this paper, we will
obtain NOR networks with a minimum number of gates for a parallel binary adder
of n-bits for an arbitrary value of n. Henceforth a network with a minimum number
of gates will be called a G-minimum network.

5. SOFTWARE IMPLEMENTATION:
 Modelsim 6.0
 Xilinx 14.2
HARDWARE IMPLEMENTATION:
 SPARTAN-III, SPARTAN-VI