Introduction to ASIC’s: Full-custom, standard-cell and Gate array based ASICs. SPLDs: PROM, PAL, GAL, PLA. FPGA and CPLD simplified architecture and applications. ASIC/FPGA Design flow, CAD tools Combinational circuit Design with Programmable logic Devices (PLDs).

1. MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG
FACULTY NAME: Mrs. B. Indira Priyadarshini
MATRUSRI
ENGINEERING COLLEGE

2. INTRODUCTION:
ASIC [“a-sick”] is an acronym for application specific integrated
circuit. As the name indicates, ASIC is a nonstandard integrated circuit that is
designed for a specific use or application. Generally an ASIC design will be
undertaken for a product that will have a large production run , and the ASIC
may contain a very large part of the electronics needed on a single integrated
circuit. Two ICs that might or might not be considered as ASICs are, a controller
chip for a PC and a chip for a modem.
UNIT-V
OUTCOMES:
After successful completion of this Unit students should be able to
Application specific integrated circuits
Design flow and tasks
Electric design automation tools
MATRUSRI
ENGINEERING COLLEGE

3. CONTENTS:
Types of ASICs
Full Custom
Semi Custom
Gate Array Based
OUTCOMES:
Students will be able to inspect how effectively ICs are embedded in package
and assembled in PCBs for different application.
MODULE-I: INTRODUCTION TO ASIC’S
MATRUSRI
ENGINEERING COLLEGE

4. Types of ASICs
MATRUSRI
ENGINEERING COLLEGE
Full-Custom ASICs: Possibly all logic cells and all mask layers customized
Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized

5. Full-Custom ASICs
MATRUSRI
ENGINEERING COLLEGE
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist or
 Existing library cells are not fast enough or
 The available pre-designed/pre-tested cells consume too much
power that a design can allow or
 The available logic cells are not compact enough to fit or
 ASIC technology is new or/and so special that no cell library exits.
 Offer highest performance and lowest cost (smallest die size) but at the
expense of increased design time, complexity, higher design cost and
higher risk.
 Some Examples: High-Voltage Automobile Control Chips, Ana-Digi
Communication Chips, Sensors and Actuators

6. Semi-Custom ASICs
MATRUSRI
ENGINEERING COLLEGE
ASICs , for which all of the logic cells are predesigned and some
(possibly all) of the mask layers are customized are called semi custom
ASICs.
• Using the predesigned cells from a cell library makes the design , much
easier.
• There are two types of semicustom ASICs
(i) Standard-cell–based ASICs (ii)Gate-array– based ASICs.
Standard-Cell based ASICs (CBIC- “sea-bick”)
 Use logic blocks from standard cell libraries, other mega-cells, full-
custom blocks, system-level macros(SLMs), functional standard
blocks (FSBs), cores etc.
 Get all mask layers customized- transistors and interconnect
 Manufacturing lead time is around 8 weeks
 Less efficient in size and performance but lower in design cost

7. Cell-based ASIC (CBIC)
MATRUSRI
ENGINEERING COLLEGE
he advantage of CBICs is that designers save time, money, and reduce risk by
using a predesigned, pretested, and pre characterized standard-cell library.
The disadvantages are the time or expense of designing or buying the
standard-cell library and the time needed to fabricate all layers of the ASIC for
each new design.

8. Gate Array based ASICs
MATRUSRI
ENGINEERING COLLEGE
•In a gate array (sometimes abbreviated GA) or gate-array based ASIC the
transistors are predefined on the silicon wafer.
•The designer chooses from a gate-array library of predesigned and pre-
characterized logic cells.
•The logic cells in a gate-array library are often called macros.
•A gate array, masked gate array, MGA, or prediffused array uses macros to
reduce turnaround time and comprises a base array made from a base cell or
primitive cell.
•Three types:
Channeled gate arrays
Channelless gate arrays
Structured gate arrays

9. Channeled gate arrays
MATRUSRI
ENGINEERING COLLEGE
Only the interconnect is customized.
The interconnect uses predefined spaces between rows of base cells.
Manufacturing lead time is between two days and two weeks

10. • A channel less gate-array or sea-of-gates (SOG) array die.
Channel less Gate Array
MATRUSRI
ENGINEERING COLLEGE
• Only the interconnect is customized.
• The interconnect uses predefined spaces between rows of base cells.
• Manufacturing lead time is around two days to two weeks.

11. • A structured or embedded gate-array die showing an embedded block in
the upper left corner
Structured Gate Array
MATRUSRI
ENGINEERING COLLEGE
• Only the interconnect is customized.
• Custom blocks (the same for each design) can be embedded.
• Manufacturing lead time is between two days and two weeks.

12. 1. In full custom design all circuitry and all interconnections are designed.
2. Gate array design contains only the interconnections designed.
3. Gate array design is faster than a prototype full-custom design.
4. ASIC stands for Application-specific integrated circuit.
5. Three types of gate arrays are present in ASIC.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

13. CONTENTS:
SPLDs
PROM
PLA
PAL
GAL
OUTCOMES:
Students will be able to implement such designs using programmable logic
MODULE-II: SPLDs
MATRUSRI
ENGINEERING COLLEGE

14. Programmable Logic Devices
MATRUSRI
ENGINEERING COLLEGE
•No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable interconnect
• A matrix of logic macro cells that usually consist of programmable array logic
followed by a flip-flop or latch

15. Programmable Logic Devices
MATRUSRI
ENGINEERING COLLEGE
PLDs are low-density devices which contain 1k – 10 k gates and are available
both in bipolar and CMOS technologies [PLA, PAL, GAL, PROM]
 CPLDs or FPGAs - FPGAs combine architecture of gate arrays with
programmability of PLDs.
User Configurable
 Contain Regular Structures - circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming Technologies
 Allow both Matrix and Row-based Architectures

16. Classification of PLDs
MATRUSRI
ENGINEERING COLLEGE
General Structure of PLD:

17. OR - PLD & AND – PLD Notation
MATRUSRI
ENGINEERING COLLEGE
Programming by blowing fuses.

18. PROM
MATRUSRI
ENGINEERING COLLEGE
• AND array with buffer/inverter is an n-to-2n- line decoder.
•OR array is a collection of programmable or-gates.
•Decoder is a min-term generator.
•n-variable min-terms appear on the 2n lines at the decoder output. These are
also known as word lines.
•n input lines called address lines, m output lines called bit lines.
•2n X m PROM

19. PROM
MATRUSRI
ENGINEERING COLLEGE
Example: There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block.
f = m(0, 1, 7)
g = m(0, 3, 6, 7)
h = m(0, 1, 3, 5, 7)

20. PLA
MATRUSRI
ENGINEERING COLLEGE
PLAs are characterized by three numbers:
•Number of input lines n
•Number of product terms that can be generated p (the number of AND gates)
•Number of output lines m
•n x p x m PLAs
A common way of specifying the connections in a PLA.
3 sections: input section, output section, T/C section.
Each product term is assigned a row in the table.
•Input section indicates connections between inputs to AND-array.
•Output section indicates connections between outputs of AND-array and
inputs to the OR-array.
•T/C section indicates how the exclusive or gates are programmed.
oT—true output is used.
oC—output should be complemented.

21. PLA
MATRUSRI
ENGINEERING COLLEGE
Exclusive-or-gate with a programmable fuse

22. PLA
MATRUSRI
ENGINEERING COLLEGE
Example:
F1’ = AB + AC + BC or F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

23. PAL
MATRUSRI
ENGINEERING COLLEGE
OR-array is fixed by the manufacturer of the device.
•PAL device is easier to program and less expensive than the PLA.
•Less flexible.
•For our examples:
o4-input, 3-output PAL device
oThree Boolean expressions can be realized in which two
expressions can have at most 3 product terms and one expression
can have at most 2 product terms.

24. PAL
MATRUSRI
ENGINEERING COLLEGE
Example: W(A, B, C, D) = Σm(2, 12, 13)
X(A, B, C, D) = Σm(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y(A, B, C, D) = Σm(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z(A, B, C, D) = Σm(1, 2, 8, 12, 13)
W = ABC’ + A’B’CD’
X = A + BCD
Y = A’B + CD + B’D’
Z = ABC’ + A’B’CD + AC’D’ + A’B’C’D =W +AC’D’ + A’B’C’D

25. PAL
MATRUSRI
ENGINEERING COLLEGE

26. Generic Array Logic (GAL)
MATRUSRI
ENGINEERING COLLEGE
•Reprogrammable AND array and fixed OR array with programmable output
logic.
•Uses E 2CMOS technology or floating gate technology. Therefore it is generic
and so many other PAL like structures can be developed.
•Very bulky but with PLDs these product is very light in weight.
•Custom or semi custom IC’s were manufactured.
•Consume lot of chip area.
•Speed of operation is less because of programmable switches or connections.
Cost effective.
•Less performance.

27. 1. The inputs in the PLD is given through AND gate.
2. A PLA is similar to a ROM in concept except that it doesn’t provide full
decoding to the variables and doesn’t generate all the minterms as in the
ROM.
3. The complex programmable logic device contains several PLD blocks and a
global interconnection matrix.
4. If a PAL has been programmed once it cannot be reprogrammed.
5. Applications of PLAs are Registered PALs, Configurable PALs, and PAL
programming.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

28. CONTENTS:
FPGA Simplified Architecture
Applications
CPLD Simplified Architecture
Applications
OUTCOMES:
Students will be able to experimentation on Hardware / software co-design on
FPGA/CPLD design
MODULE-III: FPGA and CPLD simplified
architecture and applications
MATRUSRI
ENGINEERING COLLEGE

29. Field-Programmable Gate Arrays(FPGAs)
MATRUSRI
ENGINEERING COLLEGE
•None of the mask layers are customized.
• There is a method for programming the basic logic cells and the
interconnect.
• The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours.

30. Field-Programmable Gate Arrays(FPGAs)
MATRUSRI
ENGINEERING COLLEGE

31. Field-Programmable Gate Arrays(FPGAs)
MATRUSRI
ENGINEERING COLLEGE
Based on Functional Unit/Logic Cell Structure
 Transistor Pairs
 Basic Logic Gates: NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
 Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
 Gate Density
 Chip Architecture (Routing Style)

32. Applications of FPGA
MATRUSRI
ENGINEERING COLLEGE
Implementation of random logic
•easier changes at system-level (one device is modified)
•can eliminate need for full-custom chips
Prototyping
•ensemble of gate arrays used to emulate a circuit to be manufactured
•get more/better/faster debugging done than possible with simulation
Reconfigurable hardware
•one hardware block used to implement more than one function
•functions must be mutually-exclusive in time
•can greatly reduce cost while enhancing flexibility
•RAM-based only option
Special-purpose computation engines
•hardware dedicated to solving one problem (or class of problems)
•accelerators attached to general-purpose computers

33. Complex Programmable Logic
Devices(CPLD)
MATRUSRI
ENGINEERING COLLEGE
1. Complexity of CPLD is between FPGA and PLD.
2. CPLD feature in common PLD:
Non-volatile configuration memory – does not need an external configuration
PROM.
Routing constraints. Not for large and deeply layered logic.
3. CPLD featured in common FPGA:
Large number of gates available.
Can include complicated
feedback path.

34. Applications of CPLD
MATRUSRI
ENGINEERING COLLEGE
Ideal for high performance, critical control applications.
Used in digital designs to perform the functions of boot loader.
Used for loading the configuration data of a field programmable gate array
from non-volatile memory.
Used in small design applications like address decoding.
Frequently used many applications like in cost sensitive, battery operated
portable devices due to its low size and usage of low power.

35. CPLDs vs. FPGAs
MATRUSRI
ENGINEERING COLLEGE
CPLD FPGA
• Architecture: PAL-like Gate Array-like
• Density: Low to medium Medium to high
12 22V10s or more up to 1 million gates
• Speed: Fast, predictable Application dependent
• Interconnect: Crossbar Routing
• Power Consumption: High Medium

36. 1. The FPGA refers to Field Programmable Gate Array.
2. Vertical and horizontal directions is separated by a channel in an FPGA.
3. An Antifuse programming technology is predominantly associated with
FPGAs.
4. EPROM, EEPROM, FLASH programming technologies are predominantly
associated with SPLDs and CPLDs.
5. Plastic-Leaded Chip Carrier (PLCC) type of CPLD packaging comprises
pins on all four sides that wrap around the edges of chip.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

37. CONTENTS:
ASIC/FPGA Design flow
CAD Tools
OUTCOMES:
Students will be able to
•Acquire skills in the design/verification/implementation of digital systems.
•Use some of the modern CAD tools to help with the design.
MODULE-IV: ASIC
MATRUSRI
ENGINEERING COLLEGE

38. ASIC Design Flow
MATRUSRI
ENGINEERING COLLEGE
1. Design entry : Design entry is a stage where the micro architecture is
implemented in a Hardware Description language like VHDL, Verilog ,
System Verilog etc.
2. Logic synthesis: Use an HDL (VHDL or Verilog) and a logic synthesis tool
to produce a net list a description of the logic cells and their connections
3.System partitioning : Divide a large system into ASIC sized pieces.
4. Pre-layout simulation: Check to see if the design functions correctly.
5. Floor planning: Arrange the blocks of the netlist on the chip.
6. Placement: Decide the locations of cells in a block.
7. Routing: Make the connections between cells and blocks.
8.Extraction : Determine the resistance and capacitance of the interconnect.
9. Post layout simulation. It is used to check to see whether the design still
works with the added loads of the interconnect or not

39. ASIC/FPGA Design Flow
MATRUSRI
ENGINEERING COLLEGE

40. Computer-aided-design (CAD) Tools
MATRUSRI
ENGINEERING COLLEGE
System partitioning:
• Goal: Partition a system into a number of ASICs.
• Objectives:
– Minimize the number of external connections between the ASICs.
– Keep each ASIC smaller than a maximum size.
Floor planning:
• Goal: Calculate the sizes of all the blocks and assign them locations.
• Objective: Keep the highly connected blocks physically close to each
other.
Placement:
• Goal: Assign the interconnect areas and the location of all the logic cells
within the flexible blocks.
• Objectives: Minimize the ASIC area and the interconnect density.
Global routing:
• Goal: Determine the location of all the interconnect.
• Objective: Minimize the total interconnect area used.
Detailed routing:
• Goal: Completely route all the interconnect on the chip.
• Objective: Minimize the total interconnect length used.

41. CAD Tools
MATRUSRI
ENGINEERING COLLEGE
Cadence Virtuoso platform and its functional components:
Cadence Encounter Digital IC Design
Platform:

42. CAD Tools
MATRUSRI
ENGINEERING COLLEGE
Synopsis Design Complier:
Synopsys Innovator:

43. CAD Tools
MATRUSRI
ENGINEERING COLLEGE
Function Comments Free / Low Cost Commercial
Mask Layout
general purpose VLSI and IC design
MAGIC / IRSIM
XCircuit
Microwind / Dsch
Tanner Tools
CADENCE
quick mask design Photoshop
Process Simulation
everything SUPREM-III, SUPREM-IV TSUPREM4 SSUPREM4
everything FLOODS, FLOOPS
anisotropic etching ACES
lithography PROLITH
processing and device simulator MICROTEC
Device Simulation
2D
PISCES2 MEDICI
MINIMOS
1D SimWindows
MEMS
SUGAR
NODAS
MEMSCAP
Coventorware (MEMCAD)
High Level Simulation
Verilog, VHDL as well VHDL-AMS SMASH SMASH
VHDL ModelSim XE II ModelSim
High Level
Synthesis
Xilinx ISE WebPACK
Synopsys
LeonardoSpectrum
Circuit Simulation
CaZM licensed to Tanner CaZM Tanner TSPICE
some of the programs include the
macromodeling and analog
behavioral extensions
SPICE from Berkeley
B2-Spice
WinSpice
SMASH
PSPICE
LTSpice
TopSPICE
SPECTRE
HSPICE
SMASH
PSPICE
ICAP
Graphics Postprocessor POSTMINI
Mathematical Modeling
Matrix analysis and computation MATLAB
General purpose multiphysics and
finite element analysis
ANSYS
FEMLAB

44. 1. The utilization of CAD tools for drawing timing waveform diagram and
transforming it into a network of logic gates is known as Waveform Editor.
2. Synthesis is a process of transforming design entry information of the
circuit into a set of logic equations.
3. In VLSI design, Extraction process deals with the determination of
resistance & capacitance of interconnections.
4. In Net-list language, the net-list is generated After synthesizing Verilog
code.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

45. CONTENTS:
Combinational Circuit Design with PLDs
PROM
PLA
PAL
OUTCOMES:
Students will be able to Design and optimize complex Combinational circuits.
MODULE-V: Combinational circuit Design
with Programmable logic Devices (PLDs)
MATRUSRI
ENGINEERING COLLEGE

46. BCD to Excess-3 code using PLA
E3 = ∑m (5,6,7,8,9) + ∑d (10,11,12,13,14,15)
E2 = ∑m (1,2,3,4,9) + ∑d (10,11,12,13,14,15)
E1 = ∑m (0,3,4,7,8) + ∑d (10,11,12,13,14,15)
E0 = ∑m (0,2,4,6,8) + ∑d (10,11,12,13,14,15)
Combinational circuit Design with PLDs
MATRUSRI
ENGINEERING COLLEGE

47. MATRUSRI
ENGINEERING COLLEGE
Full Adder using PROM
Sum = ∑ m (1,2,4,7)
Carry = ∑ m (3,5,6,7)
Combinational circuit Design with PLDs

48. Combinational circuit Design with PLDs
MATRUSRI
ENGINEERING COLLEGE
Example: There are 3 inputs and 2 outputs,
f1 = m(1, 2, 4, 5, 7)
f2 = m(0, 1, 3, 5, 7)
f1= y’z+xy’+xz+x’yz’
f2 = x’y’+z

49. 1. The OR array in a PAL is fixed.
2. PAL type of PLD should be used to program basic logic functions.
3. The content of a simple programmable logic device (PLD) consists of
thousands of basic logic gates and advanced sequential logic functions.
4. The basic programmable logic array (PLA) contains a set of NOT gates,
AND gates, and OR gates.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

50. CONTENTS:
ASIC Cell Libraries
OUTCOMES:
Student will able to learn how to use libraries from ASIC cell.
MODULE-VI: Additional Topic
MATRUSRI
ENGINEERING COLLEGE

51. ASIC Cell Libraries
MATRUSRI
ENGINEERING COLLEGE
Three choices:
•The ASIC vendor will supply a cell library
•Can buy a cell library from a third-party library vendor
•Can build own cell library.
Each cell in an ASIC cell library must contain:
•A physical layout
•A behavioral model
•A Verilog/VHDL model
•A detailed timing model
•A test strategy
•A circuit schematic
•A cell icon
•A wire-load model
•A routing model

52. 1. Layout of library cells is either hand-crafted or uses some form of
symbolic layout.
2. As libraries get larger, ASIC designs between different generations of
process technologies becomes more important.
3. Highest common denominator library will extract the current
manufacturing capability.
4. The optimum cell layout for each process generation changes because the
design rules for each ASIC vendor’s process are always slightly different—
even for the same generation of technology.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

53. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 List CAD tools used in circuit design. L1 CO5
2 Draw simple architecture of CPLD. L1 CO5
3 Draw FPGA architecture. L1 CO5
4 Describe types of semi-custom ASICs? L2 CO5
5 Realize 1 bit full adder using PLA. L2 CO5
6 Give the applications of FPGA. L1 CO5
7 Mention the applications of CPLD L1 CO5
8 Compare PAL, PLA and PROM L2 CO5
9 Write short notes on GAL L1 CO5

54. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1 Realize the function f = ∑(5, 7, 10, 14, 15) using PLA. L2 CO5
2 Differentite among various types of ASIC available. L2 CO5
3 Write short notes on CAD today for combinational
circuit design.
L1 CO5
4 Write short notes on PLDs L1 CO5
5 Realize the function f = ∑(4, 5, 7, 9, 13, 15) using PLA. L2 CO5
6 Draw and Explain FPGA design flow. L2 CO5
7 Explain simplified architectures of CPLD and FPGAs. L2 CO5
8 Design a PLA to realize the following three functions
and draw programming table F1 = A’B’D’ + B’CD’ +
A’BCDE’, F2 = A’BE + B’CD’E, F3 = A’B’D’ +
B’C’D’E’ + A’BCD.
L5 CO5

55. Assignment Questions
MATRUSRI
ENGINEERING COLLEGE
1. Draw and explain simplified architectures of CPLD and FPGAs.
2. Design a PLA to realize the following three functions and draw
programming table f1 =∑m(4,5,7,10), f2 =∑m(3,5,7,13).
3. Realize the gray to binary code converter using PAL.
4. Describe types of ASICs. Explain each of them.
5. Draw and Explain ASIC design flow.