This document describes an FPGA-based address generator for the deinterleaver used in WiMAX systems. It proposes algorithms to generate addresses for the deinterleaver that support different modulation schemes like QPSK, 16-QAM, and 64-QAM without using a floor function. The algorithms are implemented using VHDL on a Xilinx FPGA. Simulation results show the address generation for different modulation types matches the output of a MATLAB program. The FPGA implementation provides better performance and resource utilization than a conventional LUT-based approach.

1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 01 | Jan-2014, Available @ http://www.ijret.org 436
FPGA BASED LOW POWER AND HIGH PERFORMANCE ADDRESS
GENERATOR FOR WIMAX DEINTERLEAVER
D. Poornima Devi1
, A. Nandhini2
, S.Ellammal3
1, 2,3
Department of ECE, Sri Vidya College of Engineering and Technology Virudhunagar, India
Abstract
The main aim of this project is to generate the address generation circuitry of Deinterleaver used in the WiMAX transreceiver using
the Xilinx Field Programmable Gate Array(FPGA). The floor function associated with the implementation of FPGA is very difficult in
IEEE 802.16e standard. So we eliminate the requirement of floor function by using a simple mathematical algorithm. Some
modulations like QPSK, 16-QAM and 64-QAM along with its code rates make our approach to be novel and high efficient.
Keywords— Modulation circuits, Deinterleaver/Interleaver circuit, Wireless SYSTEMS.
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1. INTRODUCTION
IEEE has developed standards for mobile Broadband Wireless
Access popularly referred to as mobile WiMAX [1]. The
channel interleaver employed in the WiMAX transreceiver
plays a vital role in minimizing the effect of burst error [2].
In this brief, a novel, low-complexity, high-speed, and resource-
efficient address generator for the channel deinterleaver used in
the WiMAX transreceiver eliminating the requirement of floor
function is proposed. Very few works related to hardware
implementation of the project is used the
interleaver/deinterleaver used in a WiMAX system is available
in the literature. The work in [3] demonstrates the grouping of
incoming data streams into the block to reduce the frequency
of memory access in a deinterleaver using a conventional look-
up table (LUT)- based CMOS address generator for WiMAX.
A low cost and re-configurable architecture for address
computation is always beneficial. IEEE 802.16e [4] called
WiMAX is being used in the communication industry with
many variants in channel coding, like different block sizes and
different modulation schemes (e.g. BPSK, QPSK, 16-QAM and
64-QAM). System level overview for WiMAX showing use of
channel interleaver is shown in Fig. 1.
The type of interleaver used here is the block interleaver, in
which the data is written sequentially in a memory and read in a
random order after applying certain permutations. The block
interleaver can also be considered as a row-column matrix. In
this case, data is written row-wise in a memory configured as a
row-column matrix and then read column wise after applying
certain intra-row and inter-row permutations. Some work [2] –
[4] has been published for the hardware implementation of
WiMAX interleaver indifferent scenarios, but no mathematical
formulation has been proposed behind the implementation. This
paper emphasizes on reduction in complexity of the address
generation by 2-D transformation of the original interleaving
functions. Software simulation using ModelSim is performed to
verify the functionality of the proposed algorithm and
hardware. FPGA implementation results along with their
possible comparison with recent similar work have been made.
In this brief, use of FPGA’s embedded multiplier provides
performance improvement by reducing interconnection delay,
efficient resource utilization, and lesser power consumption
compared with a configurable logic block-based multiplier. Our
work shows betterment over the LUT technique to the
approximately 49% in terms of maximum operating frequency.
Fig 1 Overview of WiMAX Transreceiver
Fig 2 Interleaver/Deinterleaver Structure

2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 01 | Jan-2014, Available @ http://www.ijret.org 437
2. WiMAX CHANNEL INTERLEAVER
The mandatory blocks of a WiMAX transreceiver are shown in
Fig.1. Data stream received from a source is randomized before
being encoded by two forward error correction (FEC) coding
techniques, namely, Reed–Solomon (RS) and convolutional
coding (CC). The channel interleaver permutes the encoded bit
stream to reduce the effect of burst error. When convolutional
turbo code (CTC) is used for FEC, being optional in WiMAX,
the channel interleaver is not required; CTC itself includes an
interleaver within it [7]. Modulation and construction of the
orthogonal multiplexing symbols are performed by the two
subsequent blocks, namely, mapper and inverse fast Fourier
transform of Fig.1 In the receiver, the blocks are organized in
the reverse order enabling the restoration of the original data
sequence at the output [8].
Two dimensional block interleaver/deinterleaver structure,
which is used as a channel interleaver/deinterleaver in the
WiMAX system, is described in Fig.2.It has two memory
blocks, namely, M-1/2 and an address generator. In block
interleaving, when one memory block is being written, the
other one is read, and vice versa. When sel =1,write enabled
signal WE of M-1 is active. During this period, the input data
stream is written in M-1 as it receives the write addresses.
Simultaneously, an interleaved data stream is read fromM-2 as
it is supplied with the read addresses. After the memory blocks
are written/read up to the desired location as specified by
interleaver depth, the status of sel signal is changed to swap the
read/write operation.
2.1 Expressions for Interleaver
• The block interleaver/deinterleaver exploits different
depths ‘Ncbps’ to incorporate various code rates and
modulation schemes for IEEE 802.16e .
• The data stream received from the RS-CC encoder is
permuted by using the two-step processes described by
(1) and (2).
Here, the number of columns is represented by d (= 16/12 for
WiMAX); mk and jk are the outputs after the first and second
steps, respectively; and k varies from 0 to Ncbps − 1. s is a
parameter defined as s = Ncpc/2, where Ncpc is the number of
coded bits per the subcarrier, i.e., 2, 4, or 6 for QPSK, 16-
QAM,or 64-QAM, respectively .Modulo and floor functions.
2.2 Expressions for Deinterleaver
The deinterleaver, which performs the inverse operation, is also
defined by two permutations, i.e., (3) and (4).
Let mj and kj define the first and second level of permutations
for thedeinterleaver, where j is the index of received bits within
a block of Ncbps bits. Eqns(3) and (4) perform inverse
operation of (2) and (1), respectively.
Due to the presence of a floor function in (3) and (4), their
direct implementation on an FPGA chip is not feasible.
3. DESIGN METHODOLOGY OF ADDRESS
GENERATOR
The deinterleaver address for the first four rows and five
columns of each modulation type
• Ncbps=no.of code words=96
• J=row numbers=0,1,…….(d-1).
• i=column numbers=0,1,……..(Ncbps/d)-1.
• Kn=deinterleaver addresses.
• No.of rows=d=16(fixed)
• No.of columns=Ncbps/d=96/16=6
The following three algorithms for the three modulation
schemes are proposed. These algorithms are also tested on
MATLAB. Results obtained are verified with the previous
MATLAB program for all code rates and modulation schemes
of the WiMAX deinterleaver.
3.1 QPSK
Initialize Ncpbs and d
For j=0 to d-1, j++
For i=0 to (Ncpbs/d)-1, i++
Kn=d* i + j
end for
end for
3.2 16-QAM
Initialize Ncpbs and d
For j=0 to d-1, j++
For i=0 to (Ncpbs/d)-1, i++
If (jmod2=0)
Kn=d* i + j
else
If (imod2=0)
Kn=d*(i+1)+j
else
kn=d*(i-1)+j
end if
end if
end if
end if

3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 01 | Jan-2014, Available @ http://www.ijret.org 438
3.3 64-QAM
Initialize Ncpbs and d
For j=0 to d-1, j++
For i=0 to (Ncpbs/d)-1, i++
If (jmod3=0)
Kn=d* i + j
else if(jmod3=1)
if (imod3=2)
kn=d*(i-2)+j
else
kn=d*(i+1)+j
end if
else
if (imod3=0)
kn=d*(i+2)+j
else
kn=d*(i-1)+j
end if
end if
end if
end if
4 COMPLETE DEINTERLEAVER ADDRESS
GENERATOR
Fig. 4 Top-level view of complete deinterleaver address
generator
Our design is optimized in the sense that common logic circuits
such as multiplier, adder, rowcounter, and column counte rare
shared while generating addresses for any modulation type. In
addition, the design also shares the incrementer and the
decrementer is required in 16-QAM and 64-QAM block.
Table1. Determination of correlation between address
Table 2 Sample address for three modulation schemes
5. SIMULATION RESULTS
The proposed hardware of the address generator is converted
into a VHDL program using the Xilinx ISE. Simulation results
are obtained for all permissible modulation types and code rates
using ModelSimXE-III and apart of the same for Ncbps=
576-bits, 3/4coderate, and 64-QAM has been presented in
Fig.5. The initial portion of Fig.5shows the last part of
addresses for first row (j=1), and the latter part (fromruler)
shows the addresses for second row (j=2). The simulation
results are verified with the output obtained from the MATLAB
program.

4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 01 | Jan-2014, Available @ http://www.ijret.org 439
Fig 5 Deinterleaver Address
Fig 6 16-QAM Address
CONCLUSIONS
This brief has proposed a novel algorithm along with its
mathematical formulation, including proof for address gener-
ation circuitry of the WiMAX channel deinterleaver supporting
all possible code rates and modulation patterns as per IEEE
802.16e. The proposed algorithm is converted into an optimized
digital hardware circuit. The hardware is implemented on the
Xilinx FPGA using VHDL. Comparison of our proposed work
with a conventional LUT-based method and also with a recent
work show significant improvement on resource utilization and
operating frequency.
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