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Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
           Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                  Vol. 3, Issue 1, January -February 2013, pp.1235-1241
  Multilevel Inverter with Natural Balancing of DC Sources for PV
                         System Applications
                   Mahrous Ahmed*, Ibrahim Taha*, Sherif Ghoneim*
                                Taif University, Faculty of engineering, Taif, KSA


Abstract
         This paper presents a photovoltaic               demand from the load does not always equal the
system as a standalone system. The proposed               solar panel capacity, battery banks are generally
system consists of photovoltaic (PV) module,              used. The growing number of research in power
battery energy storage system (BESS), high                electronics has decreased the initial cost of these
frequency transformer, and multilevel inverter            system and facilitated their use around the world.
(MLI). The MLI consists of two H-bridge single                     In recent years, there has been great interest
phase inverter per arm (phase) with unequal dc            in multilevel inverters (MLIs) technology. Special
voltages which needs 6 isolated dc sources for the        attention has been paid for cascaded H-bridge
conventional MLI. The relative values between             inverter [3] – [7]. Generally, there are many
the upper (auxiliary) inverter dc voltage and the         advantages in the applications of MLIs inverters
lower H-bridge (main) inverter is 1/3 resulting in        over conventional two-level inverters. The series
9 levels MLI. Each isolated dc source comes from          connection of power converter modules reduces the
a PV module accompany with a BESS. A high                 voltage stress of each converter module (or increases
frequency transformer (HFT) is proposed in this           the voltage capability of the overall converter
paper to generate the dc bus voltage of the               structure). Besides, the resolution of the staircase
auxiliary inverter from the main inverter dc bus          waveform of the output voltage increases with the
voltage. As a result of that the number of isolated       number of voltage steps of capacitor voltage sources
dc bus voltages required is reduced by half which         available in the multilevel inverter [5]. As a result of
is reflected in reducing the number of PV                 the improved resolution in the voltage harmonic
required and thus reducing the cost of the overall        content, filtering efforts and the level of the
system. In addition, a natural balancing between          electromagnetic interference (EM) generated by the
the main and auxiliary inverters dc bus voltages          switching operation of the converter can be reduced.
of each arm will be attained due to the HFT turns                  Despite this important improvement, these
ratio which result in simplifying the overall             topologies have an important drawback: They need
control of the whole system. In order to reduce           many isolated power supplies that must be balanced.
the size of the HFT a judicious modulation index          These balanced isolated sources are generated from
(MI) will be chosen. The proposed system has              the PV system for the considered situation in this
been simulated using static inductive load.               paper. This reason, costly and complex topologies
Analyses and simulation have been proposed to             have to be implemented to get many isolated
validate the proposed control scheme.                     supplies. Some solutions using cascaded multilevel
                                                          inverters with a single power source and without
Keywords       – MLI; PV; HF Transformer;                 transformers have been introduced recently [8] – [9].
bidirectional converter; Isolated dc sources.             However, these solutions use floating capacitors
                                                          with complex balancing systems and many more
1. Introduction                                           semiconductors in relation to the number of levels
          Today world is facing a cute energy             produced.
shortage due to the increase of the average                        The objective of this paper is to develop
consumption of energy per capita. Therefore               a new dc-link topology for cascaded H-bridge
renewable energy systems are a promising                  inverter with maximum voltage resolution, based
application with great interest in clean and              on a simple High Frequency Link (HFL) with
renewable energy sources. The photovoltaic system         small size, which allows using only one power
is the second important renewable energy sources          supply (battery pack, fuel cell or other) for single
after the wind power sources. Two main applications       arm. The system has inherent regulation of the
of the PV systems, grid connected and standalone          voltages supplied among the H-bridges, so the
systems [1] – [2]. Standalone PV power systems are        full number of levels can be produced at any
electrical power systems energized by photovoltaic        amplitude of voltage, depending only on the
panels which are independent of the utility grid. In      single-dc-supply regulation per arm, which can
standalone photovoltaic power systems, the                be controlled with a chopper. This proposed
electrical energy produced by the photovoltaic            topology does not need floating capacitors or
panels cannot always be used directly. As the             heavy bulky transformers.



                                                                                                1235 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
            Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                         Vol. 3, Issue 1, January -February 2013, pp.
2. Proposed Multi-Level Inverter System            which decreases drastically its cost. Therefore the
          Figure 1 represents the schematic diagram       control of the load voltage is executed by fixing the
of the 3-phase 9-level 24-switch VSI. For                 dc inverter voltage.
convenience, all the switches and diodes have been                 Figure 2 shows the HFT that connects
considered to be ideal; moreover, voltage                 the main inverter unit with the auxiliary inverter
fluctuations of dc bus voltage also considering           unit. It composed of HFT with a two switches
absent. It has two single phase H-bridge inverters        operate in a complementary mode of operation to
modules per phase (arm). The ratio of the dc power        supply a switch dc voltage required by the
supplies is 1/3 which enables developing the              transformer. The transform is a step down with
maximum output voltage resolution. The H-bridge           3/1 turns ratio which is suitable for this specific
module with lower dc voltage source is the auxiliary      application and MLI. The main task of this HFT
inverter and the H-bridge with greater dc voltage         is to generate the dc source of the auxiliary
source is the main inverter. That is due to the load      inverter unit from the main transformer unit dc
power contribution is mainly provided from the            source. By this method, an inherit voltage
main inverter. In this topology, each phase is            balancing between the main and auxiliary
containing 2-dc sources. Which are Vdc and 3Vdc.          inverter units is obtained which is very
Therefore the maximum dc multilevel output voltage        important. This balancing will result in
level can be produced (Vdc+3Vs) =4Vdc and the             simplifying the control system. Using HFT will
minimum output level of dc voltage can be 0V.             decrease the isolated dc sources by half for this
Hence some possible options are proposed to create        MLI. In another way, each HFT is used to
(4 × 2 + 1 = 9) levels in AC voltage wave shape, if       replace a PV module which will also decrease
there are one volt level difference between every two     the cost of the whole system.
congested level.
     Table I shows the switching states and the load                               Sa11        Sa13
node voltage referred to the neutral of the dc bus
voltage ( 𝑣 𝑎𝑁 ) for Arm „a‟. The load line-to-line
voltages can be calculated as follows:                                                                         Vu
                                                                        Vdc
     𝑣 𝑎𝑏 = 𝑣 𝑎𝑁 − 𝑣 𝑏𝑁                         (1)                                Sa12        Sa14


Therefore the load line-to-line voltages can have
                                                                                                                    VaN
                                                                          3:1



(9Vdc, 8Vdc, 7Vdc, 6Vdc, 5Vdc, 4Vdc, 3Vdc, 2Vdc,1Vdc,
0Vdc,-1Vdc, -2Vdc, -3Vdc, -4Vdc, -5Vdc, -6Vdc,-7Vdc, -       HFT
                                                                                   Sa21        Sa23
8Vdc, -9Vdc) . The load phase voltages Van, Vbn and
Vcn can be calculated as in (2):
                                                                                                               Vl
      𝑣 𝑎𝑛      2  −1 −1                                                3Vdc
      𝑣 𝑎𝑛 =    −1 2 − 1                            (2)                            Sa22        Sa24                      N
      𝑣 𝑎𝑛      −1 2 − 1

As the reference voltage increases modulation index
(MI), the available levels increases. For 100% MI,
                                                          Figure 1. The conventional 9 level MLI with
the number of available levels is 9, therefore the
                                                          maximum output voltage resolution
available levels (N) can be calculated as follows:
                                                          Table I. Simple Switching Description of the
           9             𝑀𝐼 > 0.75
                                                          Proposed Model
           7      0.75 ≥ 𝑀𝐼 > 0.5
     𝑁=                                       (3)         Voltage                                                   S
           5      0.5 ≥ 𝑀𝐼 > 0.25                         level
                                                                    Sa1       Sa   Sa     Sa   Sa     Sa   Sa2
                                                                                                                    a2
           3            𝑀𝐼 < 0.25                                   1         12   13     14   21     22   3
                                                          (VaN)                                                     4
                                                          4 Vs      1         0    0      1    1      0    0        1
     The operation of this inverter has been              3 Vs      1         0    1      0    1      0    0        1
simulated for different values of MI assuming that        2 Vs      0         1    1      0    1      0    0        1
the main inverter DC voltage is 150V and the              1 Vs      1         0    0      1    0      1    1        0
auxiliary dc voltage is 50V, results have been            0 Vs      0         1    1      0    0      1    1        0
tabulated in table II. it can be concluded that for MI    - Vs      0         1    1      0    1      0    1        0
around 0.9, the auxiliary inverter contributes with a     -2 Vs     1         0    0      1    0      1    1        0
very small value of load power and the load power is      -3 Vs     1         0    1      0    0      1    1        0
                                                          -4 Vs     0         1    1      0    0      1    1        0
mainly taken from the main inverter. This means
that if the operation of the MLI has been fixed at MI
around 0.9, the rating of the HFT will be very small



                                                                                                    1236 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
                    Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                                Vol. 3, Issue 1, January -February 2013, pp.

                                     Table II. Results of the MLI with Wide Range of MI
                  Number                                                                                              Ratio      of
                  of                                                                                                  contribution
       MI         output    auxiliary inverter                      Main inverter                                     of Aux and
                  voltage                                                                                             Main
                  level                                                                                               Inverters
                            Idc[A]         Vdc [V]     Aux.         Idc[A]       Vdc [V]             Main             PMain/PAux
                                                       Power[W]                                      power[W]
       0.95       9         3              50          150          21           150                 3150             3150/150=21
       0.9        9         0.05           50          2.5          20           150                 3000             1200
       0.85       9         -2.4           50          -120         18           150                 2700             22.5
       0.8        9         -4.5           50          -225         17           150                 2550             11.33
       0.75       7         -6             50          -300         16           150                 2400             8
       0.7        7         -7             50          -350         14           150                 2100             6
       0.65       7         -7             50          -350         12           150                 1800             5.1
       0.6        7         -6.8           50          -340         11           150                 1650             4.9
       0.55       7         -5.5           50          -275         9            150                 1350             4.9
       0.5        5         -3.3           50          165          7            150                 1050             6.4
       0.45       5         0.2            50          10           4.8          150                 720              72
       0.4        5         2.5            50          125          3            150                 450              3.6
       0.35       5         4.5            50          225          1.5          150                 225              1
       0.3        5         5              50          250          0.5          150                 75               0.3
       0.25       3         4.5            50          225          0.003        150                 0.5              0.002
       0.2        3         2.7            50          135          0.003        150                 0.5              0.004

                                     HFT
                                     3:1
                                                                                        DC-DC boost
       Sa3      Sa4                                                                      converter
                                                                                                                                3Vdc
3Vdc                                             Vdc
                                                                                                               Sa1
                                                                                            To boost
                                                                       IPV
                                                                                             swicth
                                                                                 MPPT
   Figure 2. The upper MLI cell voltage is generated                  VPV                                                     Bidirectional
                                                                                                                               converter
   from the lower MLI cell                                                                               Sa2
             The dc source of the main inverter unit is                                    Battery
   generated from the PV module as shown in figure 3.
   It consists of PV module which is the main
   unregulated dc source, dc-dc converter accompany
   with maximum power point tracking control required             Figure 3. The lower MLI cell dc voltage source
   for catching the maximum available power from the              component
   PV module, and a storage battery system with a
   bidirectional dc-dc converter for regulating the dc             Discharging   Rest      Scharging       Rest       Discharging
   source at specified voltage value. To get the
   maximum power from the PV module, the
   conventional perturb and observe (P&O) [10] – [12]                                                                             Vdc_up
                                                                                                                         Hysteresis
   has been adopted in this work. A PV module of                                        Vdc
                                                                                                                           Band
   BP485 has been chosen with nominal values given in                                                                             Vdc_lw
   table III. The bidirectional control of the battery
   energy storage system (BESS) is carried out based on
   the modified hysteresis control [13] – [14] shown in           Figure 4. Modified hysteresis-control strategy
   figures 4 and 5.

    Table III. PV module BP485 specifications
   Rated Power (Pmax)            85W
   Voltage at Pmax (Vmp)         17.4V
   Current at Pmax (Imp)         4.9A
   Short circuit current (Isc)   5.48A
   Open circuit voltage (Voc)    22V


                                                                                                                     1237 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
              Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                          Vol. 3, Issue 1, January -February 2013, pp.
 Sense Vdc


                No                       No
Vdc > Vdc_up             Vdc < Vdc_lw

      Yes                      Yes

V*dc=Vdc_up              V*dc=Vdc_lw


Buck Mode                Boost Mode               Rest Mode



Figure 5. Battery-mode                  control    block       (BESS
/modified hysteresis)
                                                                                                     MLI Model

                                                                                                                           a


                                                                                1
                                                                                ..
                                                                                3


                        50 %                              S4
                                        PWM
                      Duty Cycle                          S5

                                                                       S4

                                                                   S5                                            N




                                                                                                         PWM          Fixed
                                                                                                                     MI = 0.9
                                                                                          S1



                Ipv



                           Vpv                        S3                                                 S2




                          PV Model                                                   S1    S2
                                                                                                         Vdc

          Ipv                                                                                         Voltage V*dc BESS mode
                                                                                     PWM
                      MPPT              PWM          S3                                               Control        control
         Vpv

                                                                                                Battery Model
                                              Figure 6. The proposed multi-level inverter system

3. Results and Discussions
          Figure 6 shows the integration of the above                       chosen with 100 resistance and 20 mH inductance
description of the system for single arm (phase). The                       as shown in figure 7. The dynamic response has been
proposed system has been simulated using                                    verified due to a sudden change in the load voltage. A
MATLAB/SIMULINK® to verify the performance of                               sudden change has been taken place by bubbling the
the proposed control. A nonlinear load of three phase                       load after 0.2 seconds of simulation starting. An ideal
full bridge rectifier loaded with a RL load has been



                                                                                                                     1238 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
            Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                        Vol. 3, Issue 1, January -February 2013, pp.
electronic switches and diodes have been assumed for            4

simulation.
                                                                3
          Figure 7 from top to bottom represents the
load current and voltage, respectively. It illustrates          2
that the change in the load current at 0.2 s due to
sudden decrease in the load impedance is almost one             1
                                                                0.15    0.16      0.17           0.18       0.19    0.2   0.21      0.22          0.23      0.24   0.25
half of its initial value. The average value of the load
current changed from about 1.8A to 3.6A. In the other       700
hand, the load voltage is almost constant with average
                                                            600
value of 530 V and this attributes to the voltage
control employed on the dc bus of the ML inverter.          500
          Figure 8 shows the MLI line currents. It          400
illustrates that line currents increased due to the
                                                            300
sudden decreased in the load impedance to about               0.15      0.16      0.17           0.18       0.19    0.2   0.21      0.22          0.23      0.24   0.25
twice of its value after 0.2s. Figure 9 gives the MLI
three phase line-to-line voltages. Since the operation     Figure 7. Load current and load voltage with load
of the MLI is done at constant MI besides the dc bus       step at 0.2 s.
                                                            5
voltages is kept constant using voltage control,
therefore these voltages are kept constant under the        0

dynamic change of the load.                                -5
                                                           0.18         0.185        0.19               0.195      0.2     0.205           0.21          0.215     0.22
          Figures 10 and 11 show the contribution of        5
the main, auxiliary inverters voltages and currents
                                                            0
respectively. Figure 10 shows the voltages of the
auxiliary and man voltages. It indicates that the          -5
                                                           0.18         0.185        0.19               0.195      0.2     0.205           0.21          0.215     0.22
auxiliary voltages have more switching compared to          5

the main inverter. The main inverter voltages is            0
nearly has load frequency switching. Besides the           -5
relative values between the auxiliary inverter voltage     0.18         0.185        0.19               0.195      0.2     0.205           0.21          0.215     0.22

and main inverter voltage is 1/3 which comes from          Figure 8 MLI line currents with load step at 0.2 s.
the HFT. On the other hand figure 11 shows the
current contribution of the auxiliary and main               500
inverters. Two observations can be done; 1) the first,
the auxiliary inverter current is more switched than                0

the main inverter current; 2) the second, the main
                                                            -500
inverter current is unidirectional while the auxiliary         0.18       0.185           0.19           0.195      0.2     0.205          0.21          0.215     0.22
                                                             500
inverter current is bidirectional. Due to that the
average values will follow the design given in table                0
II. This indicates that load is actually supplied from
the main inverter. Therefore this will be reflected on      -500
                                                               0.18       0.185           0.19           0.195      0.2     0.205          0.21          0.215     0.22
the size of the HFT to be very small which is a main         500
task in this work.
                                                                    0
Figure 12 illustrates the HFT input voltage. A fixed
duty cycle of 50% at 10kHz switching frequency have         -500
                                                               0.18       0.185           0.19           0.195      0.2     0.205          0.21          0.215     0.22
been used. Figure 13 shows the dc bus voltage of the
main and auxiliary inverters. The main inverter dc         Figure 9 MLI line-to-line output voltages with load
bus is about 270 V and the auxiliary inverter dc bus is    step at 0.2 s.
about 90 V. the voltage control done the battery           100

banks can guarantee to keep these dc bus voltages at        50

certain specific constant value without change with             0
load changing.                                              -50

                                                           -100
                                                              0.18       0.185           0.19           0.195      0.2     0.205           0.21          0.215     0.22


                                                           400

                                                           200

                                                                0

                                                           -200

                                                           -400
                                                              0.18       0.185           0.19           0.195      0.2     0.205           0.21          0.215     0.22

                                                           Figure 10 MLI upper and lower cell voltages.



                                                                                                                                 1239 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
                                    Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                                                Vol. 3, Issue 1, January -February 2013, pp.
                                                                                                                 Simulation results have been provided for system
        4                                                                                                        verification.A conclusion might elaborate on the
        2                                                                                                        importance of the work or suggest applications
        0                                                                                                        and extensions.
      -2

      -4
      0.18        0.185         0.19         0.195      0.2        0.205         0.21          0.215      0.22
                                                                                                                 Acknowledgements
                                                                                                                          The authors would like to acknowledge the
        4                                                                                                        Taif University project. The research has been
        3                                                                                                        carried out under the Project no. 1-433-2049.
        2

        1                                                                                                        References
      0
                                                                                                                   [1]   Soeren Baekhoej Kjaer, John K. Pedersen,
      0.18        0.185         0.19         0.195      0.2        0.205         0.21          0.215      0.22
                                                                                                                         and Frede Blaabjerg, “A Review of Single-
                Figure 11 upper and lower MLI cells currents.                                                            Phase     Grid-Connected      Inverters   for
                                                                                                                         Photovoltaic Modules” IEEE Transactions
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                the proposed topology are; 1) it has lower number                                                        M., “Investigation on Capacitor Voltage
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                                                                                                                                                     1240 | P a g e
Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering
         Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
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PV system MLI reduces DC sources

  • 1. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1235-1241 Multilevel Inverter with Natural Balancing of DC Sources for PV System Applications Mahrous Ahmed*, Ibrahim Taha*, Sherif Ghoneim* Taif University, Faculty of engineering, Taif, KSA Abstract This paper presents a photovoltaic demand from the load does not always equal the system as a standalone system. The proposed solar panel capacity, battery banks are generally system consists of photovoltaic (PV) module, used. The growing number of research in power battery energy storage system (BESS), high electronics has decreased the initial cost of these frequency transformer, and multilevel inverter system and facilitated their use around the world. (MLI). The MLI consists of two H-bridge single In recent years, there has been great interest phase inverter per arm (phase) with unequal dc in multilevel inverters (MLIs) technology. Special voltages which needs 6 isolated dc sources for the attention has been paid for cascaded H-bridge conventional MLI. The relative values between inverter [3] – [7]. Generally, there are many the upper (auxiliary) inverter dc voltage and the advantages in the applications of MLIs inverters lower H-bridge (main) inverter is 1/3 resulting in over conventional two-level inverters. The series 9 levels MLI. Each isolated dc source comes from connection of power converter modules reduces the a PV module accompany with a BESS. A high voltage stress of each converter module (or increases frequency transformer (HFT) is proposed in this the voltage capability of the overall converter paper to generate the dc bus voltage of the structure). Besides, the resolution of the staircase auxiliary inverter from the main inverter dc bus waveform of the output voltage increases with the voltage. As a result of that the number of isolated number of voltage steps of capacitor voltage sources dc bus voltages required is reduced by half which available in the multilevel inverter [5]. As a result of is reflected in reducing the number of PV the improved resolution in the voltage harmonic required and thus reducing the cost of the overall content, filtering efforts and the level of the system. In addition, a natural balancing between electromagnetic interference (EM) generated by the the main and auxiliary inverters dc bus voltages switching operation of the converter can be reduced. of each arm will be attained due to the HFT turns Despite this important improvement, these ratio which result in simplifying the overall topologies have an important drawback: They need control of the whole system. In order to reduce many isolated power supplies that must be balanced. the size of the HFT a judicious modulation index These balanced isolated sources are generated from (MI) will be chosen. The proposed system has the PV system for the considered situation in this been simulated using static inductive load. paper. This reason, costly and complex topologies Analyses and simulation have been proposed to have to be implemented to get many isolated validate the proposed control scheme. supplies. Some solutions using cascaded multilevel inverters with a single power source and without Keywords – MLI; PV; HF Transformer; transformers have been introduced recently [8] – [9]. bidirectional converter; Isolated dc sources. However, these solutions use floating capacitors with complex balancing systems and many more 1. Introduction semiconductors in relation to the number of levels Today world is facing a cute energy produced. shortage due to the increase of the average The objective of this paper is to develop consumption of energy per capita. Therefore a new dc-link topology for cascaded H-bridge renewable energy systems are a promising inverter with maximum voltage resolution, based application with great interest in clean and on a simple High Frequency Link (HFL) with renewable energy sources. The photovoltaic system small size, which allows using only one power is the second important renewable energy sources supply (battery pack, fuel cell or other) for single after the wind power sources. Two main applications arm. The system has inherent regulation of the of the PV systems, grid connected and standalone voltages supplied among the H-bridges, so the systems [1] – [2]. Standalone PV power systems are full number of levels can be produced at any electrical power systems energized by photovoltaic amplitude of voltage, depending only on the panels which are independent of the utility grid. In single-dc-supply regulation per arm, which can standalone photovoltaic power systems, the be controlled with a chopper. This proposed electrical energy produced by the photovoltaic topology does not need floating capacitors or panels cannot always be used directly. As the heavy bulky transformers. 1235 | P a g e
  • 2. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. 2. Proposed Multi-Level Inverter System which decreases drastically its cost. Therefore the Figure 1 represents the schematic diagram control of the load voltage is executed by fixing the of the 3-phase 9-level 24-switch VSI. For dc inverter voltage. convenience, all the switches and diodes have been Figure 2 shows the HFT that connects considered to be ideal; moreover, voltage the main inverter unit with the auxiliary inverter fluctuations of dc bus voltage also considering unit. It composed of HFT with a two switches absent. It has two single phase H-bridge inverters operate in a complementary mode of operation to modules per phase (arm). The ratio of the dc power supply a switch dc voltage required by the supplies is 1/3 which enables developing the transformer. The transform is a step down with maximum output voltage resolution. The H-bridge 3/1 turns ratio which is suitable for this specific module with lower dc voltage source is the auxiliary application and MLI. The main task of this HFT inverter and the H-bridge with greater dc voltage is to generate the dc source of the auxiliary source is the main inverter. That is due to the load inverter unit from the main transformer unit dc power contribution is mainly provided from the source. By this method, an inherit voltage main inverter. In this topology, each phase is balancing between the main and auxiliary containing 2-dc sources. Which are Vdc and 3Vdc. inverter units is obtained which is very Therefore the maximum dc multilevel output voltage important. This balancing will result in level can be produced (Vdc+3Vs) =4Vdc and the simplifying the control system. Using HFT will minimum output level of dc voltage can be 0V. decrease the isolated dc sources by half for this Hence some possible options are proposed to create MLI. In another way, each HFT is used to (4 × 2 + 1 = 9) levels in AC voltage wave shape, if replace a PV module which will also decrease there are one volt level difference between every two the cost of the whole system. congested level. Table I shows the switching states and the load Sa11 Sa13 node voltage referred to the neutral of the dc bus voltage ( 𝑣 𝑎𝑁 ) for Arm „a‟. The load line-to-line voltages can be calculated as follows: Vu Vdc 𝑣 𝑎𝑏 = 𝑣 𝑎𝑁 − 𝑣 𝑏𝑁 (1) Sa12 Sa14 Therefore the load line-to-line voltages can have VaN 3:1 (9Vdc, 8Vdc, 7Vdc, 6Vdc, 5Vdc, 4Vdc, 3Vdc, 2Vdc,1Vdc, 0Vdc,-1Vdc, -2Vdc, -3Vdc, -4Vdc, -5Vdc, -6Vdc,-7Vdc, - HFT Sa21 Sa23 8Vdc, -9Vdc) . The load phase voltages Van, Vbn and Vcn can be calculated as in (2): Vl 𝑣 𝑎𝑛 2 −1 −1 3Vdc 𝑣 𝑎𝑛 = −1 2 − 1 (2) Sa22 Sa24 N 𝑣 𝑎𝑛 −1 2 − 1 As the reference voltage increases modulation index (MI), the available levels increases. For 100% MI, Figure 1. The conventional 9 level MLI with the number of available levels is 9, therefore the maximum output voltage resolution available levels (N) can be calculated as follows: Table I. Simple Switching Description of the 9 𝑀𝐼 > 0.75 Proposed Model 7 0.75 ≥ 𝑀𝐼 > 0.5 𝑁= (3) Voltage S 5 0.5 ≥ 𝑀𝐼 > 0.25 level Sa1 Sa Sa Sa Sa Sa Sa2 a2 3 𝑀𝐼 < 0.25 1 12 13 14 21 22 3 (VaN) 4 4 Vs 1 0 0 1 1 0 0 1 The operation of this inverter has been 3 Vs 1 0 1 0 1 0 0 1 simulated for different values of MI assuming that 2 Vs 0 1 1 0 1 0 0 1 the main inverter DC voltage is 150V and the 1 Vs 1 0 0 1 0 1 1 0 auxiliary dc voltage is 50V, results have been 0 Vs 0 1 1 0 0 1 1 0 tabulated in table II. it can be concluded that for MI - Vs 0 1 1 0 1 0 1 0 around 0.9, the auxiliary inverter contributes with a -2 Vs 1 0 0 1 0 1 1 0 very small value of load power and the load power is -3 Vs 1 0 1 0 0 1 1 0 -4 Vs 0 1 1 0 0 1 1 0 mainly taken from the main inverter. This means that if the operation of the MLI has been fixed at MI around 0.9, the rating of the HFT will be very small 1236 | P a g e
  • 3. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. Table II. Results of the MLI with Wide Range of MI Number Ratio of of contribution MI output auxiliary inverter Main inverter of Aux and voltage Main level Inverters Idc[A] Vdc [V] Aux. Idc[A] Vdc [V] Main PMain/PAux Power[W] power[W] 0.95 9 3 50 150 21 150 3150 3150/150=21 0.9 9 0.05 50 2.5 20 150 3000 1200 0.85 9 -2.4 50 -120 18 150 2700 22.5 0.8 9 -4.5 50 -225 17 150 2550 11.33 0.75 7 -6 50 -300 16 150 2400 8 0.7 7 -7 50 -350 14 150 2100 6 0.65 7 -7 50 -350 12 150 1800 5.1 0.6 7 -6.8 50 -340 11 150 1650 4.9 0.55 7 -5.5 50 -275 9 150 1350 4.9 0.5 5 -3.3 50 165 7 150 1050 6.4 0.45 5 0.2 50 10 4.8 150 720 72 0.4 5 2.5 50 125 3 150 450 3.6 0.35 5 4.5 50 225 1.5 150 225 1 0.3 5 5 50 250 0.5 150 75 0.3 0.25 3 4.5 50 225 0.003 150 0.5 0.002 0.2 3 2.7 50 135 0.003 150 0.5 0.004 HFT 3:1 DC-DC boost Sa3 Sa4 converter 3Vdc 3Vdc Vdc Sa1 To boost IPV swicth MPPT Figure 2. The upper MLI cell voltage is generated VPV Bidirectional converter from the lower MLI cell Sa2 The dc source of the main inverter unit is Battery generated from the PV module as shown in figure 3. It consists of PV module which is the main unregulated dc source, dc-dc converter accompany with maximum power point tracking control required Figure 3. The lower MLI cell dc voltage source for catching the maximum available power from the component PV module, and a storage battery system with a bidirectional dc-dc converter for regulating the dc Discharging Rest Scharging Rest Discharging source at specified voltage value. To get the maximum power from the PV module, the conventional perturb and observe (P&O) [10] – [12] Vdc_up Hysteresis has been adopted in this work. A PV module of Vdc Band BP485 has been chosen with nominal values given in Vdc_lw table III. The bidirectional control of the battery energy storage system (BESS) is carried out based on the modified hysteresis control [13] – [14] shown in Figure 4. Modified hysteresis-control strategy figures 4 and 5. Table III. PV module BP485 specifications Rated Power (Pmax) 85W Voltage at Pmax (Vmp) 17.4V Current at Pmax (Imp) 4.9A Short circuit current (Isc) 5.48A Open circuit voltage (Voc) 22V 1237 | P a g e
  • 4. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. Sense Vdc No No Vdc > Vdc_up Vdc < Vdc_lw Yes Yes V*dc=Vdc_up V*dc=Vdc_lw Buck Mode Boost Mode Rest Mode Figure 5. Battery-mode control block (BESS /modified hysteresis) MLI Model a 1 .. 3 50 % S4 PWM Duty Cycle S5 S4 S5 N PWM Fixed MI = 0.9 S1 Ipv Vpv S3 S2 PV Model S1 S2 Vdc Ipv Voltage V*dc BESS mode PWM MPPT PWM S3 Control control Vpv Battery Model Figure 6. The proposed multi-level inverter system 3. Results and Discussions Figure 6 shows the integration of the above chosen with 100 resistance and 20 mH inductance description of the system for single arm (phase). The as shown in figure 7. The dynamic response has been proposed system has been simulated using verified due to a sudden change in the load voltage. A MATLAB/SIMULINK® to verify the performance of sudden change has been taken place by bubbling the the proposed control. A nonlinear load of three phase load after 0.2 seconds of simulation starting. An ideal full bridge rectifier loaded with a RL load has been 1238 | P a g e
  • 5. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. electronic switches and diodes have been assumed for 4 simulation. 3 Figure 7 from top to bottom represents the load current and voltage, respectively. It illustrates 2 that the change in the load current at 0.2 s due to sudden decrease in the load impedance is almost one 1 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 half of its initial value. The average value of the load current changed from about 1.8A to 3.6A. In the other 700 hand, the load voltage is almost constant with average 600 value of 530 V and this attributes to the voltage control employed on the dc bus of the ML inverter. 500 Figure 8 shows the MLI line currents. It 400 illustrates that line currents increased due to the 300 sudden decreased in the load impedance to about 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 twice of its value after 0.2s. Figure 9 gives the MLI three phase line-to-line voltages. Since the operation Figure 7. Load current and load voltage with load of the MLI is done at constant MI besides the dc bus step at 0.2 s. 5 voltages is kept constant using voltage control, therefore these voltages are kept constant under the 0 dynamic change of the load. -5 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 Figures 10 and 11 show the contribution of 5 the main, auxiliary inverters voltages and currents 0 respectively. Figure 10 shows the voltages of the auxiliary and man voltages. It indicates that the -5 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 auxiliary voltages have more switching compared to 5 the main inverter. The main inverter voltages is 0 nearly has load frequency switching. Besides the -5 relative values between the auxiliary inverter voltage 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 and main inverter voltage is 1/3 which comes from Figure 8 MLI line currents with load step at 0.2 s. the HFT. On the other hand figure 11 shows the current contribution of the auxiliary and main 500 inverters. Two observations can be done; 1) the first, the auxiliary inverter current is more switched than 0 the main inverter current; 2) the second, the main -500 inverter current is unidirectional while the auxiliary 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 500 inverter current is bidirectional. Due to that the average values will follow the design given in table 0 II. This indicates that load is actually supplied from the main inverter. Therefore this will be reflected on -500 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 the size of the HFT to be very small which is a main 500 task in this work. 0 Figure 12 illustrates the HFT input voltage. A fixed duty cycle of 50% at 10kHz switching frequency have -500 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 been used. Figure 13 shows the dc bus voltage of the main and auxiliary inverters. The main inverter dc Figure 9 MLI line-to-line output voltages with load bus is about 270 V and the auxiliary inverter dc bus is step at 0.2 s. about 90 V. the voltage control done the battery 100 banks can guarantee to keep these dc bus voltages at 50 certain specific constant value without change with 0 load changing. -50 -100 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 400 200 0 -200 -400 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 Figure 10 MLI upper and lower cell voltages. 1239 | P a g e
  • 6. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. Simulation results have been provided for system 4 verification.A conclusion might elaborate on the 2 importance of the work or suggest applications 0 and extensions. -2 -4 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 Acknowledgements The authors would like to acknowledge the 4 Taif University project. The research has been 3 carried out under the Project no. 1-433-2049. 2 1 References 0 [1] Soeren Baekhoej Kjaer, John K. Pedersen, 0.18 0.185 0.19 0.195 0.2 0.205 0.21 0.215 0.22 and Frede Blaabjerg, “A Review of Single- Figure 11 upper and lower MLI cells currents. Phase Grid-Connected Inverters for Photovoltaic Modules” IEEE Transactions 300 on Industry Applications, Vol. 41, No. 5, 250 September/October, 2005, pp: 1292 – 1306. 200 [2] Eduardo Román, Ricardo Alonso, Pedro Ibañez, Sabino Elorduizapatarietxe, and Damián Goitia, “Intelligent PV Module for 150 100 Grid-Connected PV Systems”, IEEE 50 Transactions on Industrial Electronics, Vol. 53, No. 4, August 2006, pp: 1066 – 1073. 0 [3] M. N. A. Kadir S. Mekhilef, and H. W. Ping -50 0.199 0.1992 0.1994 0.1996 0.1998 0.2 0.2002 0.2004 0.2006 0.2008 0.201 Voltage Vector Control of a Hybrid Three- Figure 12 High frequency transformer input voltage. Stage Eighteen-Level Inverter by Vector Decomposition IET Transaction on Power 400 Electronics, Volume 3, Issue 4, pp.601- 611, [4] Saad Mekhilef, and Mohamad N. Abdul 200 Kadir, “Novel Vector Control Method for 0 Three-Stage Hybrid Cascaded Multilevel Inverter”, IEEE Transactions On Industrial -200 0 0.05 0.1 0.15 0.2 0.25 0.3 Electronics, Vol. 58, No. 4, April 2011. [5] Samir Kouro, Rafael Bernal, Hernán 150 Miranda, César A. Silva, and José 100 Rodríguez, “High-Performance Torque and 50 Flux Control for Multilevel Inverter Fed 0 Induction Motors”, IEEE Transactions on -50 0 0.05 0.1 0.15 0.2 0.25 0.3 Power Electronics, Vol. 22, No. 6, November 2007, pp: 2116 – 2123. Figure 13 Lower and upper MLI DC input voltages. [6] Baruschka, L.; Mertens, A., “Comparison of Cascaded H-Bridge and Modular Multilevel 8. Conclusions Converters for BESS application”, IEEE This paper presented simulation, analysis Energy Conversion Congress and Exposition and the operation of MLI inverter for standalone (ECCE), 2011, pp: 909 – 916. PV system applications. The main advantages of [7] Sepahvand, H.; Jingsheng Liao; Ferdowsi, the proposed topology are; 1) it has lower number M., “Investigation on Capacitor Voltage of isolated dc bus voltages, 2) the dc bus voltages Regulation in Cascaded H-Bridge Multilevel of the main and auxiliary inverters are naturally Converters With Fundamental Frequency balanced due to using the HFT. In this system a Switching”, IEEE Transactions on Industrial HFT is used per phase to generate the dc bus Electronics, Vol.: 58 , Issue: 11, 2011, pp: voltage of the auxiliary inverter from the dc bus 5102 – 5111. of the main inverters. A fixed and optimum MI is [8] D. Zhong, B. Ozpineci, L. M. Tolbert, and J. chosen to reduce drastically the HFT which is N. Chiasson, “DC-AC Cascaded H-Bridge very important in reducing the overall system Multilevel Boost Inverter With No Inductors size. The dynamic performance of the system is for Electric/Hybrid Electric Vehicle tested due to a sudden change in the load voltage. Applications,” Industry Applications, IEEE A voltage control technique is employed to keep Transactions on, vol. 45, no. 3,2009, pp. the dc bus voltage constant where a PV 963-970. accompany with a BESS is used for this task. 1240 | P a g e
  • 7. Mahrous Ahmed, Ibrahim Taha, Sherif Ghoneim / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp. [9] S. Vazquez, J. I. Leon, L. G. Franquelo, J. J. Padilla, and J. M. Carrasco, “DC-Voltage- Ratio Control Strategy for Multilevel Cascaded Converters Fed With a Single DC Source,” Industrial Electronics, IEEE Transactions on, vol. 56, no. 7, 2009, pp. 2513-2521. [10] Femia, N.; Petrone, G.; Spagnuolo, G.; Vitelli, M., “Optimization of perturb and observe maximum power point tracking method”, IEEE Transactions on Power Electronics, Vol. 20 , Issue: 4, 2005 , pp: 963 – 973. [11] Chee Wei Tan; Green, T.C.; Hernandez- Aramburo, C.A, “Analysis of perturb and observe maximum power point tracking algorithm for photovoltaic applications”, IEEE 2nd International Power and Energy Conference, PECon 2008, pp: 237 – 242. [12] Elgendy, M. A.; Zahawi, B.; Atkinson, D. J., “Evaluation of perturb and observe MPPT algorithm implementation techniques”, 6th IET International Conference on Power Electronics, Machines and Drives (PEMD 2012), 2012 , pp: 1 – 6. [13] Seul-Ki Kim, Jin-Hong Jeon, Chang-Hee Cho, Jong-Bo Ahn, and Sae-Hyuk Kwon, “Dynamic Modeling and Control of a Grid- Connected Hybrid Generation System With Versatile Power Transfer”, IEEE Transactions on Industrial Electronics, Vol. 55, No. 4, April, 2008, pp: 1677- 1688. 1241 | P a g e